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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * * * * * * Office electronics Instrumentation and measuring equipment Machine tools Audiovisual equipment Home appliance Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * * * * Aerospace equipment Communications equipment for trunk lines Control equipment for the nuclear power industry Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. Please direct all queries regarding the products covered herein to a sales representative of the company.
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Contents 1. Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Simultaneous Operation Modes Allowed with Four Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Identifier Codes and OTP Address for Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Identifier Codes and OTP Address for Read Operation on Partition Configuration . . . . . . . . . . . . . . . . . . . . . . 10 5.4 OTP Block Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Functions of Block Lock and Block Lock-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 Block Locking State Transitions upon Command Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Block Locking State Transitions upon F-WP Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. Status Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Write Cycle (F-WE / F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance . . . . . . . . . . . . . . . . . . . 12.5 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13. AC Electrical Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 SRAM AC Characteristics Timing Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 21 22 23 26 27 27 27 28 29
14. Data Retention Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15. Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16. Flash Memory Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18. Related Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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1. Description The LRS1381 is a combination memory organized as 2,097,152 x16 bit flash memory and 262,144 x16 bit static RAM in one package. Features - Power supply - Operating temperature - Not designed or rated as radiation hardened - 72pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon Flash Memory - Access Time Read Word write Block erase Reset Power-Down Standby - Optimized Array Blocking Architecture Eight 4K-word Parameter Blocks Sixty-Three 32K-word Main Blocks Bottom Parameter Location - Extended Cycling Capability 100,000 Block Erase Cycles (F-VPP = 2.7V to 3.3V) 1,000 Block Erase Cycles and total 80 hours (F-VPP = 11.7V to 12.3V) - Enhanced Automated Suspend Options Word Write Suspend to Read Block Erase Suspend to Word Write Block Erase Suspend to Read - OTP Block 4 Word + 4 Word Array SRAM - Access Time - Power Supply current Operating current Standby current Data retention current
**** ****
2.7V to 3.3V -25C to +85C
**** **** **** **** **** ****
85 ns 25 mA 60 mA 30 mA 25 A 25 A
(Max.) (Max. tCYCLE = 200ns, CMOS Input) (Max.) (Max.) (Max. F-RST = GND 0.2V, IOUT (F-RY/BY) = 0mA) (Max. F-CE = F-RST = F-VCC 0.2V)
- Power supply current (The current for F-VCC pin and F-VPP pin)
**** **** **** **** ****
70 ns 50 mA 8 mA 25 A 25 A
(Max.) (Max. tRC, tWC = Min.) (Max. tRC, tWC = 1s, CMOS Input) (Max.) (Max. S-VCC = 3.0V)
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2. Pin Configuration INDEX (TOP View)
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Pin A0 to A16 F-A17 to F-A20 S-A17 F-CE S-CE1, S-CE2 F-WE S-WE F-OE S-OE S-LB S-UB Address Inputs (Common) Address Inputs (Flash) Address Input (SRAM) Chip Enable Inputs (Flash) Chip Enable Inputs (SRAM) Write Enable Input (Flash) Write Enable Input (SRAM) Output Enable Input (Flash) Output Enable Input (SRAM)
Description
Type Input Input Input Input Input Input Input Input Input Input Input
SRAM Byte Enable Input (DQ0 to DQ7) SRAM Byte Enable Input (DQ8 to DQ15) Reset Power Down Input (Flash) Block erase and Write : VIH Read : VIH Reset Power Down : VIL Write Protect Input (Flash) When F-WP is VIL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and locked-down. When F-WP is VIH, lock-down is disabled. Ready/Busy Output (Flash) During an Erase or Write operation : VOL Block Erase and Write Suspend : High-Z (High impedance) Data Inputs and Outputs (Common) Power Supply (Flash) Power Supply (SRAM) Monitoring Power Supply Voltage (Flash) Block Erase and Write : F-VPP = VPPH1/2 All Blocks Locked : F-VPP < VPPLK GND (Common) Non Connection (Should be all open) Test pins (Should be all open)
F-RST
Input
F-WP
Input
F-RY/BY DQ0 to DQ15 F-VCC S-VCC F-VPP GND NC T1 to T 3
Open Drain Output Input / Output Power Power Input Power -
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3. Truth Table 3.1 Bus operation(1) Flash Read Output Disable Write Read Standby Output Disable Write Read Reset Power Output Down Disable Write Standby Reset Power Standby Down Notes: Standby SRAM Notes 3,5 5 2,3,4,5 5 5 5 5,6 5,6 5,6 5 5,6 H X H L X X (8) X X X X High-Z X L X X L H H H X X L H L H F-CE F-RST F-OE F-WE S-CE1 S-CE2 S-OE S-WE S-LB S-UB DQ to DQ 0 15 L H H L L H X X L H X X H H X L H H X L X H X H (9) X H X H (9) (9) High-Z (9) High-Z (8) X X X X (7) High-Z DIN
1. L = VIL, H = VIH, X = H or L. High-Z = High impedance. Refer to the DC Characteristics. 2. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when F-VPP = VPPH1/2 and F-VCC = 2.7V to 3.3V. Block erase, full chip erase, (page buffer) program or OTP program with F-VPP < VPPH1/2 (Min.) produce spurious results and should not be attempted. 3. Never hold F-OE low and F-WE low at the same timing. 4. Refer Section 5. Command Definitions for Flash Memory valid DIN during a write operation. 5. F-WP set to VIL or VIH. 6. Electricity consumption of Flash Memory is lowest when F-RST = GND 0.2V. 7. Flash Read Mode Mode Read Array Read Identifier Codes/OTP Read Query 8. SRAM Standby Mode S-CE1 S-CE2 S-LB S-UB H X X X L X X X H X X H Address X See 5.2, 5.3 Refer to the Appendix DQ0 to DQ15 DOUT See 5.2, 5.3 Refer to the Appendix
9. S-UB, S-LB Control Mode S-LB S-UB DQ0 to DQ7 L L H L H L DOUT/DIN DOUT/DIN High-Z
DQ8 to DQ15 DOUT/DIN High-Z DOUT/DIN
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3.2 Simultaneous Operation Modes Allowed with Four Planes(1, 2) THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE PARTITION IS: Read Array Read ID/OTP Read Status Read Query Word Program Page Buffer Program OTP Program Block Erase Full Chip Erase Program Suspend Block Erase Suspend Notes: 1. "X" denotes the operation available. 2. Configurative Partition Dual Work Restrictions: Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command queuing except page buffer program. Commands must be written to an address within the block targeted by that command. X X X X X X Read Array X X X X X X Read ID/OTP X X X X X X Read Status X X X X X X X X X X X X X X X X X X Read Query X X X X X X Page Word OTP Buffer Program Program Program X X X X X X X X X Block Erase X X X X X Full Chip Erase Program Suspend X X X X Block Erase Suspend X X X X X X
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4. Block Diagram
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5. Command Definitions for Flash Memory(11) 5.1 Command Definitions Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit Clear Block Lock Bit Set Block Lock-down Bit OTP Program Set Partition Configuration Register Notes: 1. Bus operations are defined in 3.1 Bus operation. 2. First bus cycle command address should be the same as the second cycle address. X=Any valid address within the device. PA=Address within the selected partition. IA=Identifier codes address (See 5.2, 5.3). QA=Query codes address. Refer to the LH28F320BX, LH28F640BX series Appendix for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. OA=Address of OTP block to be read or programmed (See 5.4 OTP Block Address Map). PCRC=Partition configuration register code presented on the address A0-A15. 3. ID=Data read from identifier codes. (See 5.2, 5.3 ). QD=Data read from query database. Refer to the LH28F320BX, LH28F640BX series Appendix for details. SRD=Data read from status register. See 6. Status Register Definition for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first). OD=Data to be programmed at location OA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first). N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within OTP block (See 5.2, 5.3 ). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when F-RST is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. Bus Cycles Req'd 1 2 2 2 1 2 2 2 4 1 1 2 2 2 2 2 First Bus Cycle Notes 2 2,3,4 2,3,4 2,3 2 2,3,5 2,5,9 2,3,5,6 2,3,5,7 2,8,9 2,8,9 2 2,10 2 2,3,9 2,3 Oper(1) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address(2) PA PA PA PA PA BA X WA WA PA PA BA BA BA OA PCRC Data(3) FFH 90H 98H 70H 50H 20H 30H 40H or 10H E8H B0H D0H 60H 60H 60H C0H 60H Write Write Write Write Write BA BA BA OA PCRC 01H D0H 2FH OD 04H Write Write Write Write BA X WA WA D0H D0H WD N-1 Read Read Read IA or OA ID or OD QA PA QD SRD Second Bus Cycle Oper(1) Address(2) Data(3)
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7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target partition to be programmed and the confirm command (D0H). Refer to the LH28F320BX, LH28F640BX series Appendix for details. 8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while the block erase operation is being suspended. 10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when F-WP is VIL. When F-WP is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
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5.2 Identifier Codes and OTP Address for Read Operation Code Manufacturer Code Device Code Manufacturer Code 32M Bottom Parameter Device Code Block is Unlocked Block is Locked Block Lock Configuration Code Block is not Locked-Down Block is Locked-Down Device Configuration Code OTP Notes: 1. The address A20-A16 to read the manufacturer, device, lock configuration, device configuration code and OTP data are shown in below table. 2. Bottom parameter device has its parameter blocks in the plane 0 (The lowest address). 3. DQ15-DQ2 is reserved for future implementation. 4. PCRC=Partition Configuration Register Code. 5. OTP-LK=OTP Block Lock configuration. 6. OTP=OTP Block data. 5.3 Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) Partition Configuration Register PCR.10 0 0 0 1 0 1 1 1 PCR.9 0 0 1 0 1 1 0 1 PCR.8 0 1 0 0 1 0 1 1 00H 00H or 08H 00H or 10H 00H or 18H 00H or 08H or 10H 00H or 10H or 18H 00H or 08H or 18H 00H or 08H or 10H or 18H Address (32M-bit device) [A20-A16] Partition Configuration Register OTP Lock OTP 0006H 0080H 0081-0088H Block Address +2 Address [A15-A0](1) 0000H 0001H Data [DQ15-DQ0] 00B0H 00B5H DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 PCRC OTP-LK OTP 2 3 3 3 3 4 5 6 Notes
Notes: 1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read Identifier Codes/OTP command (90H).
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5.4 OTP Block Address Map
5.5 Functions of Block Lock(1) and Block Lock-Down Current State State [000] [001] [011] [100] [101]
(4) (4)
F-WP 0 0 0 1 1 1 1
DQ1(2) 0 0 1 0 0 1 1
DQ0(2) 0 1 1 0 1 0 1 Locked
State Name Unlocked
Erase/Program Allowed (3) Yes No No Yes No Yes No
Locked-down Unlocked Locked Lock-down Disable Lock-down Disable
[110](5) [111] Note:
1. OTP (One Time Program) block has the lock function which is different from those described above. 2. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked. DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down. 3. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 4. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (F-WP = 0) or [101] (F-WP = 1), regardless of the states before power-off or reset operation. 5. When F-WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked.
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5.6 Block Locking State Transitions upon Command Write(4) Current State State [000] [001] [011] [100] [101] [110] [111] Note: 1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lockdown" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written. 4. In this state transitions table, assumes that F-WP is not changed and fixed VIL or VIH. 5.7 Block Locking State Transitions upon F-WP Transition(4) Current State Previous State State [110](2) Other than [110](2) Note: 1. "F-WP = 0 1" means that F-WP is driven to VIH and "F-WP = 1 0" means that F-WP is driven to VIL. 2. State transition from the current state [011] to the next state depends on the previous state. 3. When F-WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. [000] [001] [011] [100] [101] [110] [111] F-WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 F-WP = 0 1(1) [100] [101] [110] [111] F-WP = 1 0(1) [000] [001] [011](3) [011] Result after F-WP Transition (Next State) F-WP 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 Result after Lock Command Written (Next State) Set Lock(1) [001] No Change(3) No Change [101] No Change [111] No Change Clear Lock(1) No Change [000] No Change No Change [100] No Change [110] Set Lock-down(1) [011](2) [011] No Change [111](2) [111] [111](2) No Change
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6. Status Register Definition Status Register Definition R 15 WSMS 7 R 14 BESS 6 R 13 BEFCES 5 R 12 PBPOPS 4 Notes: Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. R 11 VPPS 3 R 10 PBPSS 2 R 9 DPS 1 R 8 R 0
SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) 1 = Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM STATUS (PBPOPS) 1 = Error in (Page Buffer) Program or OTP Program 0 = Successful (Page Buffer) Program or OTP Program SR.3 = F-VPP STATUS (VPPS) 1 = F-VPP LOW Detect, Operation Abort 0 = F-VPP OK SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked
Check SR.7 or F-RY/BY to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit or set read/partition configuration register attempt, an improper command sequence was entered.
SR.3 does not provide a continuous indication of F-VPP level. The WSM interrogates and indicates the F-VPP level only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. SR.3 is not guaranteed to report accurate feedback when F-VPP VPPH1/2 or VPPLK.
SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and should SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) be masked out when polling the status register.
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R 15 SMS 7
R 14 R 6
R 13 R 5
Extended Status Register Definition R R 12 R 4 Notes: 11 R 3
R 10 R 2
R 9 R 1
R 8 R 0
XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
After issue a Page Buffer Program command (E8H), XSR.7=1 indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register.
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R 15 R 7
R 14 R 6
R 13 R 5
Partition Configuration Register Definition R R PC2 12 R 4 11 R 3 10 R 2
PC1 9 R 1
PC0 8 R 0
PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R)
PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) 001 = Plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively. 100 = Plane 0-2 are merged into one partition. (default in a top parameter device) Notes: 011 = Plane 2-3 are merged into one partition. There are 1. After power-up or device reset, PCR10-8 (PC2-0) is set three partitions in this configuration. Dual work to "001" in a bottom parameter device and "100" in a top operation is available between any two partitions. parameter device. 110 = Plane 0-1 are merged into one partition. There are 2. See the table below for more details. three partitions in this configuration. Dual work 3. PCR.15-11 and PCR.7-0 bits are reserved for future use. operation is available between any two partitions. If these bits are read via the Read Identifier Codes/OTP 101 = Plane 1-2 are merged into one partition. There are command, the device may output "1" or "0" on these bits. three partitions in this configuration. Dual work operation is available between any two partitions. Partition Configuration
111 = There are four partitions in this configuration. Each plane corresponds to each partition respectively. Dual work operation is available between any two partitions.
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7. Memory Map for Flash Memory
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8. Absolute Maximum Ratings Symbol VCC VIN TA TSTG F-VPP Notes: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except F-VPP. 3. -2.0V undershoot and VCC +2.0V overshoot are allowed when the pulse width is less than 20 nsec. 4. VIN should not be over VCC +0.3V. 5. Applying 12V 0.3V to F-VPP during erase/write can only be done for a maximum of 1000 cycles on each block. F-VPP may be connected to 12V 0.3V for total of 80 hours maximum. +12.6V overshoot is allowed when the pulse width is less than 20 nsec. 9. Recommended DC Operating Conditions (TA = -25C to +85C) Symbol VCC VIH VIL Notes: 1. VCC is the lower of F-VCC or S-VCC. 2. VCC is the higher of F-VCC or S-VCC. 3. VCC includes both F-VCC and S-VCC. 10. Pin Capacitance(1) (TA = 25C, f = 1MHz) Symbol CIN CI/O Note: 1. Sampled but not 100% tested. Parameter Input capacitance I/O capacitance Notes Min. Typ. Max. 15 25 Unit pF pF Condition VIN = 0V VI/O = 0V Parameter Supply Voltage Input Voltage Input Voltage Notes 3 Min. 2.7 VCC -0.4 (2) -0.2 Typ. 3.0 Max. 3.3 VCC +0.2 (1) 0.4 Unit V V V Parameter Supply voltage Input voltage Operating temperature Storage temperature F-VPP voltage 1,3,5 Notes 1,2 1,2,3,4 -0.2 -0.2 -25 -55 -0.2 Ratings to to to to to +3.9 VCC +0.3 +85 +125 +12.6 Unit V V C C V
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11. DC Electrical Characteristics(1) DC Electrical Characteristics (TA = -25C to +85C, VCC = 2.7V to 3.3V) Symbol ILI ILO ICCS Parameter Input Load Current Output Leakage Current F-VCC Standby Current 2 4 Notes Min. Typ. Max. 2 2 20 Unit A A A Test Conditions VIN = VCC or GND VOUT = VCC or GND F-VCC = F-VCC Max., F-CE = F-RST = F-VCC 0.2V, F-WP = F-VCC or GND F-VCC = F-VCC Max., F-CE = GND 0.2V, F-WP = F-VCC or GND F-RST = GND 0.2V IOUT (F-RY/BY) = 0mA
ICCAS
F-VCC Automatic Power Savings Current F-VCC Reset Power-Down Current Average F-VCC Read Current Normal Mode Average F-VCC 8 Word Read Read Current Page Mode F-VCC (Page Buffer) Program Current F-VCC Block Erase, Full Chip Erase Current F-VCC (Page Buffer) Program or Block Erase Suspend Current F-VPP Standby or Read Current F-VPP (Page Buffer) Program Current F-VPP Block Erase, Full Chip Erase Current F-VPP (Page Buffer) Program Suspend Current F-VPP Block Erase Suspend Current
2,5
4
20
A
ICCD
2
4
20
A
2
15
25
mA
ICCR
2 2,6 2,6 2,6 2,6 2,3 2,7 2,6,7 2,6,7 2,6,7 2,6,7 2,7 2,7 2,7 2,7
5 20 10 10 5 10 2 2 10 2 5 2 10 2 10
10 60 20 30 15 200 5 5 30 5 15 5 200 5 200
mA mA mA mA mA A A A mA A mA A A A A
F-VCC = F-VCC Max., F-CE = VIL, F-OE = VIH , f = 5MHz IOUT = 0mA
ICCW ICCE ICCWS ICCES IPPS IPPR IPPW IPPE IPPWS
F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-CE = VIH F-VPP F-VCC
F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2 F-VPP = VPPH1 F-VPP = VPPH2
IPPES
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DC Electrical Characteristics (Continue) (TA = -25C to +85C, VCC = 2.7V to 3.3V) Symbol ISB ISB1 ICC1 Parameter S-VCC Standby Current S-VCC Standby Current S-VCC Operation Current Notes Min. Typ. (1) Max. 2 25 3 50 Unit A mA Conditions S-CE1, S-CE2 S-CE2 0.2V S-CE2 = VIL tCYCLE = Min II/O = 0mA S-VCC - 0.2V or
S-CE1 = VIL, mA S-CE2 = VIH VIN = VIL or VIH mA V V V V IOL = 0.5mA IOH = -0.5mA
ICC2 VIL VIH VOL VOH VPPLK VPPH1 VPPH2 VLKO
S-VCC Operation Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage F-VPP Lockout during Normal Operations F-VPP during Block Erase, Full Chip Erase, Word Write or Lock-Bit configuration Operations F-VCC Lockout Voltage 6 6 6 6 4,6,7 1.65 7 11.7 1.5 3 12 VCC -0.2 -0.2 VCC -0.4
8 0.4 VCC +0.2 0.4
S-CE1 0.2V, S-CE S-VCC -0.2V, tCYCLE = 1A II/O = 0mA VIN S-VCC -0.2V or 0.2V
0.4 3.3 12.3
V V V V
Notes: 1. VCC includes both F-VCC and S-VCC. 2. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA=+25 C. 3. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 4. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when F-VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.) , between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.). 5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 6. Sampled, not 100% tested. 7. F-VPP is not used for power supply pin. With F-VPP VPPLK, block erase, full chip erase, (page buffer) program and OTP program cannot be executed and should not be attempted. Applying 12V 0.3V to F-VPP provides fast erasing or fast programming mode. In this mode, F-VPP is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the VCC power bus. Applying 12V 0.3V to F-VPP during erase/program can only be done for a maximum of 1000 cycles on each block. F-VPP may be connected to 12V 0.3V for a total of 80 hours maximum.
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12. AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load 0 V to 2.7 V 5 ns 1.35 V 1TTL + CL (50pF)
12.2 Read Cycle (TA = -25C to +85C, F-VCC = 2.7V to 3.3V) Symbol tAVAV tAVQV tELQV tAPA tGLQV tPHQV tEHQZ, tGHQZ tELQX tGLQX tOH Note: 1. Sampled, not 100% tested. 2. F-OE may be delayed up to tELQV tGLQV after the falling edge of F-CE without impact to tELQV. Read Cycle Time Address to Output Delay F-CE to Output Delay Page Address Access Time F-OE to Output Delay F-RST High to Output Delay F-CE or F-OE to Output in High - Z, Whichever Occurs First F-CE to Output in Low - Z F-OE to Output in Low - Z Output Hold from First Occurring Address, F-CE or F-OE change 1 1 1 1 0 0 0 2 2 Parameter Notes Min. 85 85 85 30 20 150 20 Max. Unit ns ns ns ns ns ns ns ns ns ns
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12.3 Write Cycle (F-WE / F-CE Controlled)(1,2) (TA = -25C to +85C, F-VCC = 2.7V to 3.3V) Symbol tPHWL (tPHEL) tELWL (tWLEL) Parameter F-RST High Recovery to F-WE (F-CE) Going Low F-CE (F-WE) Setup to F-WE (F-CE) Going Low Notes 3 4 4 8 8 Min. 150 0 60 40 50 0 0 0 5 3 3 30 0 200 30 3, 6 3, 6 3, 7 3 0 0 tAVQV+40 100 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWLWH (tELEH) F-WE (F-CE) Pulse Width tDVWH (tDVEH) Data Setup to F-WE (F-CE) Going High tAVWH (tAVEH) Address Setup to F-WE (F-CE) Going High tWHEH (tEHWH) F-CE (F-WE) Hold from F-WE (F-CE) High tWHDX (tEHDX) Data Hold from F-WE (F-CE) High tWHAX (tEHAX) Address Hold from F-WE (F-CE) High tWHWL (tEHEL) F-WE (F-CE) Pulse Width High tSHWH (tSHEH) F-WP High Setup to F-WE (F-CE) Going High tVVWH (tVVEH) F-VPP Setup to F-WE (F-CE) Going High tWHGL (tEHGL) Write Recovery before Read tQVSL tQVVL tWHR0 (tEHR0) F-WP High Hold from Valid SRD, F-RY/BY High - Z F-VPP Hold from Valid SRD, F-RY/BY High - Z F-WE (F-CE) High to SR.7 Going "0"
tWHRL (tEHRL) F-WE (F-CE) High to F-RY/BY Going Low Notes:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP program operations are the same as during read-only operations. See the AC Characteristics for read cycle. 2. A write operation can be initiated and terminated with either F-CE or F-WE. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling edge of F-CE or F-WE (whichever goes low last) to the rising edge of F-CE or F-WE (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH . 5. Write pulse width high (tWPH) is defined from the rising edge of F-CE or F-WE (whichever goes high first) to the falling edge of F-CE or F-WE (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. F-VPP should be held at F-VPP=VPPH1/2 until determination of block erase, full chip erase, (page buffer) program or OTP program success (SR.1/3/4/5=0). 7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns. 8. See 5.1 Command Definitions for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit configuration.
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12.4 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(4) (TA = -25C to +85C, F-VCC = 2.7V to 3.3V) Page Buffer Command Notes is Used or not Used 2 2, 3 2 2, 3 2 2, 3 2 2 2 5 5 Not Used Used Not Used Used Not Used Used Not Used F-VPP=VPPH1 (In System) Min. Typ.
(1)
Symbol
Parameter
F-VPP=VPPH2 (In Manufacturing)
(2)
Unit
(2)
Max.
Min.
Typ.
(1)
Max.
tWPB tWMB
4K-Word Parameter Block Program Time 32K-Word Main Block Program Time
0.05 0.03 0.38 0.24 11 7 36 0.3 0.6 5 5
0.3 0.12 2.4 1 200 100 400 4 5 10 20
0.04 0.02 0.31 0.17 9 5 27 0.2 0.5 5 5
0.12 0.06 1 0.5 185 90 185 4 5 10 20
s s s s s s s s s s s
tWHQV1/ Word Program Time tEHQV1 tWHOV1/ OTP Program Time tEHOV1 tWHQV2/ 4K-Word Parameter Block tEHQV2 Erase Time tWHQV3/ 32K-Word Main Block tEHQV3 Erase Time tWHRH1/ (Page Buffer) Program Suspend tEHRH1 Latency Time to Read tWHRH2/ Block Erase Suspend tEHRH2 Latency Time to Read tERES Notes: Latency Time from Block Erase Resume Command to Block Erase Suspend Command
6
-
500
500
s
1. Typical values measured at TA=+25 C and nominal voltages. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Every 16 words data are loaded alternatively into 2 page buffers. 4. Sampled, but not 100% tested. 5. A latency time is required from writing suspend command (F-WE or F-CE going high) until SR.7 going "1"or F-RY/BY going High-Z. 6. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished.
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12.5 Flash Memory AC Characteristics Timing Chart AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code
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AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks
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AC Waveform for Write Operations(F-WE / F-CE Controlled)
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12.6 Reset Operations (TA = -25C to +85C, F-VCC = 2.7V to 3.3V) Symbol tPLPH tPLRH tVPH tVHQV Parameter F-RST Low to Reset during Read (F-RST should be low during power-up.) F-RST Low to Reset during Erase or Program F-VCC 2.7V to F-RST High F-VCC 2.7V to Output Delay Notes 1, 2, 3 1, 3, 4 1, 3, 5 3 100 1 Min. 100 22 Max. Unit ns s ns ms
Notes: 1. A reset time, tPHQV, is required from the later of SR.7 (F-RY/BY) going "1" (High-Z) or F-RST going high until outputs are valid. See the AC Characteristics - read cycle for tPHQV. 2. 4. tPLPH is <100ns the device may still reset but this is not guaranteed. 3. Sampled, not 100% tested. If F-RST asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding F-RST low minimum 100ns is required after F-VCC has been in predefined range and also has been in stable there. AC Waveform for Reset Operation
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13. AC Electrical Characteristics for SRAM 13.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load Note: 1. Including scope and socket capacitance. 13.2 Read Cycle (TA = -25C to +85C, S-VCC = 2.7V to 3.3V) Symbol tRC tAA tACE1 tACE2 tBE tOE tOH tLZ1 tLZ2 tOLZ tBLZ tHZ1 tHZ2 tOHZ tBHZ Note: 1. Active output to High-Z and High-Z to output active tests specified for a 200mV transition from steady state levels into the test load. Read Cycle Time Address access time Chip enable access time (S-CE1) Chip enable access time (S-CE2) Byte enable access time Output enable to output valid Output hold from address change S-CE1 Low to output active S-CE2 High to output active S-OE Low to output active S-UB or S-LB Low to output active S-CE1 High to output in High-Z S-CE2 Low to output in High-Z S-OE High to output in High-Z S-UB or S-LB High to output in High-Z 10 1 1 1 1 1 1 1 1 10 10 5 5 0 0 0 0 25 25 25 25 Parameter Notes Min. 70 70 70 70 70 40 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.4V to 2.4V 5ns 1.4 V 1TTL + CL (30pF)(1)
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13.3 Write Cycle (TA = -25C to +85C, S-VCC = 2.7V to 3.3V) Symbol tWC tCW tAW tBW tAS tWP tWR tDW tDH tOW tWZ Note: 1. Active output to High-Z and High-Z to output active tests specified for a 200mV transition from steady state levels into the test load. Write cycle time Chip enable to end of write Address valid to end of write Byte select time Address setup time Write pulse width Write recovery time Input data setup time Input data hold time S-WE High to output active S-WE Low to output in High-Z 1 1 Parameter Notes Min. 70 60 60 60 0 50 0 30 0 5 0 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns
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13.4 SRAM AC Characteristics Timing Chart Read Cycle Timing Chart
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Write Cycle Timing Chart (S-WE Controlled)
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Write Cycle Timing Chart (S-CE Controlled)
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Write Cycle Timing Chart (S-UB, S-LB Controlled)
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14. Data Retention Characteristics for SRAM (TA = -25C to +85C) Symbol VCCDR Parameter Data Retention Supply voltage Note 2 Min. 1.5 Typ.(1) Max. 3.3 Unit V S-CE2 S-CE1 Conditions 0.2V or S-VCC - 0.2V
ICCDR tCDR tR
Data Retention Supply current Chip enable setup time Chip enable hold time
2 0 tRC
2
25
A ns ns
S-VCC = 3.0V S-CE2 0.2V or S-CE1 S-VCC - 0.2V
Notes 1. Reference value at TA = 25C, S-VCC = 3.0V. 2. S-CE1 S-VCC - 0.2V, S-CE2 S-VCC - 0.2V (S-CE1 controlled) or S-CE2 0.2V (S-CE2 controlled).
Data Retention timing chart (S-CE1 Controlled)(1)
Data Retention timing chart (S-CE2 Controlled)
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15. Notes This product is a stacked CSP package that a 32M (x16) bit Flash Memory and a 4M (x16) bit SRAM are assembled into. - Supply Power Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3V. - Power Supply and Chip Enable of Flash Memory and SRAM (F-CE, S-CE1, S-CE2) S-CE1 should not be "low" and S-CE2 should not be "high" when F-CE is "low" simultaneously. If the two memories are active together, possibly they may not operate normally by interference noises or data collision on DQ bus. Both F-VCC and S-VCC are needed to be applied by the recommended supply voltage at the same time expect SRAM data retention mode. - Power Up Sequence When turning on Flash memory power supply, keep F-RST "low". After F-VCC reaches over 2.7V, keep F-RST "low" for more than 100nsec. - Device Decoupling The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2).
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16. Flash Memory Data Protection Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as false commands and causes undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: The below describes data protection method. 1. Protection of data in each block * ny locked block by setting its block lock bit is protected against the data alternation. When F-WP is VIL, any lockeddown block by setting its block lock-down bit is protected from lock status changes. By using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks). * For detailed block locking scheme, see Chapter 5.Command Definitions for Flash Memory. 2. Protection of data with F-VPP control * When the level of F-VPP is lower than VPPLK (F-VPP lockout voltage), write functions to all blocks including OTP block are disabled. All blocks are locked and the data in the blocks are completely protected. 3. Protection of data with F-RST * Especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing F-RST to VIL, which inhibits write operation to all blocks including OTP block. * For detailed description on F-RST control, see Chapter 12.6. AC Electrical Characteristics for Flash Memory, Reset Operations Protection against noises on F-WE signal To prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on F-WE signal.
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17. Design Considerations 1. Power Supply Decoupling To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a 0.1F ceramic capacitor connected between its F-VCC and GND and between its F-VPP and GND. Low inductance capacitors should be placed as close as possible to package leads. 2. F-VPP Trace on Printed Circuit Boards Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the F-VPP Power Supply trace. Use similar trace widths and layout considerations given to the FVCC power bus. 3. The Inhibition of Overwrite Operation Please do not execute reprograming "0" for the bit which has already been programed "0". Overwrite operation may generate unerasable bit. In case of reprograming "0" to the data which has been programed "1". * Program "0" for the bit in which you want to change data from "1" to "0". * Program "1" for the bit which has already been programed "0". For example, changing data from "1011110110111101" to "1010110110111100" requires "1110111111111110" programing. 4. Power Supply Block erase, full chip erase, word write and lock-bit configuration with an invalid F-VPP (See Chapter 11. DC Electrical Characteristics) produce spurious results and should not be attempted. Device operations at invalid F-VCC voltage (See Chapter 11. DC Electrical Characteristics) produce spurious results and should not be attempted. 18. Related Document Information(1) Document No. FUM00701 Note: 1. International customers should contact their local SHARP or distribution sales offices. Document Name LH28F320BX, LH28F640BX Series Appendix
i A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "AC Electrical Characteristics for Flash Memory" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
Symbol tVR tR tF NOTES: F-VCC Rise Time
Parameter
Notes 1 1, 2 1, 2
Min. 0.5
Max. 30000 TBD TBD
Unit s/V
Input Signal Rise Time Input Signal Fall Time
1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. tR (Max.) and tF (Max.) for F-RP (F-RST) are TBD.
Rev. 1.10
iii A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Figure A-2. Waveform for Glitch Noises
See the "DC Electrical Characteristics" described in specifications for VIH (Min.) and VIL (Max.).
Rev. 1.10
iv A-2 RELATED DOCUMENT INFORMATION(1)
Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E
Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, VPP Electric Potential Switching Circuit
NOTE: 1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Fax: (360) 834-8903 http://www.sharpsma.com
SHARP Microelectronics Europe Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Fax: (49) 40 2376-2232 http://www.sharpsme.com
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: +81-743-65-1321 Fax: +81-743-65-1532 http://www.sharp.co.jp
APPENDIX No. FU M00701 ISSUE: Jan. 18, 2001
Page Mode Dual Work Flash Memory
32M-bit, 64M-bit LH28F320BX, LH28F640BX Series
Appendix
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Appendix to Spec No.: MFM2-J13318 Model No.: LRS1381 March 16, 2001
FUM00701
Handle this appendix carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). Office electronics Instrumentation and measuring equipment Machine tools Audiovisual equipment Home appliance Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. Control and safety devices for airplanes, trains, automobiles, and other transportation equipment Mainframe computers Traffic control systems Gas leak detectors and automatic cutoff devices Rescue and security equipment Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. Aerospace equipment Communications equipment for trunk lines Control equipment for the nuclear power industry Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. Please direct all queries regarding the products covered herein to a sales representative of the company.
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CONTENTS
PAGE 1 Introduction.............................................................. 2 1.1 Features ............................................................. 2 1.2 Definition of Block, Plane and Partition........... 2 1.3 Product Overview ............................................. 2 1.4 Product Description........................................... 8 1.4.1 Memory Block Organization ..................... 8 1.4.2 Four Physical Planes .................................. 8 1.4.3 Partition ...................................................... 8 1.4.4 Parameter Block ......................................... 8 1.4.5 Main Block................................................. 8 1.4.6 OTP (One Time Program) block................ 8 2 Principles of Operation .......................................... 14 2.1 Operation Mode after Power-up or Reset Mode ............................................. 14 2.2 Read, Program and Erase Operation ............... 14 2.3 Status Register for Each Partition ................... 14 2.4 Data Protection................................................ 14 3 Bus Operation ........................................................ 15 3.1 Read Array ...................................................... 15 3.2 Output Disable ................................................ 15 3.3 Standby............................................................ 15 3.4 Reset................................................................ 15 3.5 Read Identifier Codes/OTP............................. 16 3.6 Read Query ..................................................... 16 3.7 Write the Command to the CUI ...................... 16 4 Command Definitions ............................................ 18 4.1 Read Array Command .................................... 18 4.2 Read Identifier Codes/OTP Command ........... 18 4.3 Read Query Command.................................... 23 4.4 Read Status Register Command...................... 23 4.5 Clear Status Register Command ..................... 23 4.6 Block Erase Command.................................... 26 4.7 Full Chip Erase Command.............................. 26 4.8 Program Command ......................................... 31 4.9 Page Buffer Program Command ..................... 31 4.10 Block Erase Suspend Command and Block Erase Resume Command ........... 37 4.11 (Page Buffer) Program Suspend Command and (Page Buffer) Program Resume Command ...................................... 39 4.12 Set Block Lock Bit Command ...................... 41
PAGE 4.13 Clear Block Lock Bit Command................... 4.14 Set Block Lock-Down Bit Command ........... 4.15 OTP Program Command............................... 4.16 Set Read Configuration Register Command .................................................... 4.16.1 Device Read Configuration.................... 4.16.2 Frequency Configuration ....................... 4.16.3 Data Output Configuration..................... 4.16.4 WAIT# Configuration............................ 4.16.5 Burst Sequence....................................... 4.16.6 Clock Configuration............................... 4.16.7 Burst Wrap ............................................. 4.16.8 Burst Length........................................... 4.16.8.1 Continuous Burst Length ................ 4.17 Set Partition Configuration Register Command .................................................... 4.17.1 Partition Configuration .......................... 5 Design Considerations ........................................... 5.1 Hardware Design Considerations.................... 5.1.1 Control using RST#, CE# and OE# ......... 5.1.2 Power Supply Decoupling ....................... 5.1.3 VPP Traces on Printed Circuit Boards..... 5.1.4 VCC, VPP, RST# Transitions.................. 5.1.5 Power-Up/Down Protection..................... 5.1.6 Power Dissipation .................................... 5.1.7 Automatic Power Savings........................ 5.1.8 Reset Operation........................................ 5.2 Software Design Considerations..................... 5.2.1 WSM (Write State Machine) Polling....... 5.2.2 Attention to Program Operation............... 5.3 Data Protection Method .................................. 5.4 High Performance Read Mode........................ 5.4.1 CPU Compatibility................................... 5.4.2 Features of ADV# and CLK .................... 5.4.3 Address Latch .......................................... 5.4.4 Using Asynchronous Page Mode............. 5.4.5 Using Synchronous Burst Mode .............. 5.4.6 Using WAIT# in Burst Mode................... 5.4.7 Single Read Mode.................................... 6 Common Flash Interface........................................ 7 Related Document Information.............................. 44 44 46 49 49 51 51 52 52 52 52 52 52 55 55 57 57 57 57 57 57 58 58 58 58 59 59 59 59 60 60 60 60 60 61 61 61 67 68
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1 Introduction
This appendix describes how to use the LH28F320BX/ LH28F640BX series, Synchronous/Page Mode Dual Work Flash memory. Section 1 outlines the LH28F320BX/LH28F640BX series. Sections 2, 3, 4 and 5 describe the memory organization and functionality. When designing a specific system, take into design considerations described in Section 5. Plane # Plane 0 Plane 1 Plane 2 Plane 3
Table 1. Address Range of Each Plane Contains the Blocks within the following Address 32M bit 000000H-07FFFFH 080000H-0FFFFFH 100000H-17FFFFH 180000H-1FFFFFH 64M bit 000000H-0FFFFFH 100000H-1FFFFFH 200000H-2FFFFFH 300000H-3FFFFFH
1.1 Features
Synchronous/Page Mode Dual Work Flash memory LH28F320BX/LH28F640BX series has the following features: * Dual work operation * Flexible partition configuration * High performance asynchronous reads and synchronous burst reads * Page buffer program * Individual block locking and all blocks locked on power-up * 8-word OTP (One Time Program) block * Low power consumption * Parameter block architecture
1.3 Product Overview
Synchronous/Page Mode Dual Work Flash memory LH28F320BX/LH28F640BX series is capable of dual work operation: erase or program operation on one partition and read operation on other partitions (see Table 2). The partition to be accessed is automatically identified according to the input address. Dual work operations can be achieved by dividing the memory array into four physical planes as shown in Figure 2.1 through Figure 3.2. Each plane is exactly one quarter of the entire memory array. The device has also virtual partitions. Several planes can be flexibly merged to one partition by writing the Set Partition Configuration Register command. This feature allows the user to read from one partition even though one of the other partitions is executing an erase or program operation. If the device is set to the 4 partitions configuration, each partition is exactly the same as each physical plane. After power-up or device reset, plane 0-2 are merged into one partition for top parameter devices and plane1-3 are merged into one partition for bottom parameter devices. During dual work operation, read operations to the partition being erased or programmed access the status register which indicates whether the erase or program operation is successfully completed or not. Dual work operation cannot be executed during full chip erase and OTP program mode. Memory array data can be read in two ways, that is, asynchronous 8-word page mode or synchronous burst mode. The default after power-up or device reset is the asynchronous read mode in which 8-word page mode is available. The user must set the read configuration register to enable the synchronous burst mode by writing the Set Read Configuration Register command. CLK is then used to increment the internal burst address generator, synchronize with the host, and deliver data every clock cycle. The WAIT# output pin is used to signal
1.2 Definition of Block, Plane and Partition
Block, Plane and Partition are defined and used in this document as explained below. * Block Main Block: 32K Words. Parameter Block: 4K Words. 32M-bit device has 8 parameter blocks and 63 main blocks. 64M-bit device has 8 parameter blocks and 127 main blocks. * Plane: 32M-bit and 64M-bit devices are divided into four physical planes (see Table 1). Plane0 or Plane3 contains parameter blocks and main blocks. Plane1 and Plane2 consist of only main blocks. * Partition: Read operation can be done in one partition while Program/Erase operation is being done in another partition. Partition contains at least one plane or up to four planes. Partition boundaries can be flexibly set to any plane boundary by the Set Partition Configuration Register command. If the partition configuration register is set to "111" (4 plane dual work mode), the partition is exactly the same as a plane. See Section 4.17 for more information.
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that a burst is in progress. The synchronous burst feature cannot cross partition boundaries. The LH28F320BX/LH28F640BX series contains a page buffer of 16-word 2 plane. In the page buffer program mode, the data to be programmed is first stored into the page buffer before being transferred to the memory array. A page buffer program has high speed program performance. The page buffer program operation programs up to 16 word 2 data at sequential addresses within one block. That is, this operation cannot be used to program data at addresses separated by something even in the same block, or divided into different blocks. Page buffer program cannot be applied to OTP block described later in this section. For the parameter blocks and main blocks, individual block locking scheme that allows any block to be locked, unlocked or locked-down with no latency. The time required for block locking is less than the minimum command cycle time (minimum time from the rising edge of CE# or WE# to write the command to the next rising edge of CE# or WE#). The block is locked via the Set Block Lock Bit command or Set Block Lock-down bit command. Block erase, full chip erase and (page buffer) program operation cannot be executed for locked block, to protect codes and data from unwanted operation due to noises, etc. When the WP# pin is at VIL, the locked-down block cannot be unlocked. When WP# pin is at VIH, lockdown bits are disabled and any block can be locked or unlocked through software. After WP# goes VIL, any block previously marked lock-down revert to that state. At power-up or device reset, all blocks default to locked state and are not locked-down, regardless of the states before power-off or reset operation. This means that all write operations on any block are disabled. Unauthorized use of cellular phone, communication device, etc. can be avoided by storing a security code into the 8-word OTP (One Time Program) block (see Figure 4) provided in addition to the parameter and main blocks. To ensure high reliability, a lock function for the OTP block is provided. The LH28F320BX/LH28F640BX series has a VPP pin which monitors the level of the power supply voltage. When VPP VPPLK, memory contents cannot be altered and the data in all blocks are completely write protected (see Note 1) . Note that the VPP is used only for checking the supply voltage, not used for device power supply pin.
Automatic Power Savings (APS) is the low power features to help increase battery life in portable applications. APS mode is initiated shortly after read cycle completion. In this mode, its current consumption decreases to the value equivalent of that in the standby mode. Standard address access timings (t AVQV) provide new data when addresses are changed. During dual work operation (one partition being erased or programmed, while other partitions are read modes), the device cannot enter the Automatic Power savings mode if the input address remains unchanged. A CUI (Command User Interface) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. LH28F320BX/LH28F640BX series uses an advanced WSM (Write State Machine) to automatically execute erase and program operations within the memory array. The WSM is controlled through the CUI. By writing a valid command sequence to the CUI, the WSM is instructed to automatically handle the sequence of internal events and timings required to block erase, full chip erase, (page buffer) program or OTP program operations. Status registers are prepared for each partition to indicate the status of the partition. Even if the WSM is occupied by executing erase or program operation in one partition, the status register of other partition reports that the device is not busy when the device is set to 2, 3 or 4 partitions configuration. When the RST# pin is at VIL, reset mode is enabled which minimizes power consumption and provides write protection. The RST# is also useful for resetting the WSM to read array mode and initializing the status register bits to "80H". During power-on/off or transitions, keep the RST# pin at VIL level to protect the data from noises, and initialize the device's internal control circuit.
(Note 1) Please note following: * For the lockout voltage VPPLK to inhibit all write functions, refer to specifications. * VPP should be kept lower than VPPLK (GND) during read operations to protect the data in all blocks.
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A reset time (t PHQV) is required from RST# switching high until outputs are valid. Likewise, the device has a wake time (t PHWL, tPHEL) from RST#-high until writes to the CUI are recognized. Erase operation erases one block or all blocks. Programming is executed in either one word increments or by page sized increments using the high speed program page buffers. These operations use an industry standard set of CUI command sequences. Suspend commands exist for both the erase and program operations to permit the system to interrupt an erase or program operation in progress to enable the access to another memory location
in the same partition. Nested suspend is also supported. This allows the software to suspend an erase in one partition, start programming in a second partition, suspend programming in the second partition, then read from the second partition. After reading from the second partition, resume the suspended program in the second partition, then resume the suspended erase in the first partition. Figure 1 shows the block diagram for LH28F320BX/ LH28F640BX series. The example of pin descriptions are explained in Table 3.1 and Table 3.2.
Table 2. Simultaneous Operation Modes Allowed with Four Planes(1, 2) THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE PARTITION IS: Read Array Read ID/OTP Read Status Read Query Word Program Page Buffer Program OTP Program Block Erase Full Chip Erase Program Suspend Block Erase Suspend X X X X X X Read Read Read Array ID/OTP Status X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Read Word Query Program X X X X X X X X X X Block Page OTP Block Full Chip Program Erase Buffer Program Erase Erase Suspend Suspend Program X X X X X X X X X X X X X X X X X X X X
NOTES: 1. "X" denotes the operation available. 2. Configurative Partition Dual Work Restrictions: Status register reflects partition state, not WSM(Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command queuing except page buffer program. Commands must be written to an address within the block targeted by that command. It is not possible to do burst reads that cross partition boundaries.
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Figure 1. Block Diagram
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Table 3.1. Pin Descriptions Symbol A0-A20 A0-A21 Type INPUT INPUT Name and Function ADDRESS INPUTS: Inputs for addresses. 32M: A0-A20 ADDRESS INPUTS: Inputs for addresses. 64M: A0-A21 DATA INPUT/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query, identifier code and device configuration code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle. Chip Enable: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to standby levels. CLOCK: Synchronizes the memory to the system bus operating frequency in synchronous burst mode. The first rising (or falling if RCR.6 is "0") edge latches the address when ADV# is VIL or upon a rising ADV# edge. This is used only for synchronous burst mode. ADDRESS VALID: Addresses are input to the memory when ADV# is low (VIL). Addresses are latched on ADV#'s rising edge during read and write operations. RESET: When low (VIL), RST# resets internal automation and inhibits write operations which provides data protection. RST#-high (VIH) enables normal operation. After power-up or reset mode, the device is automatically set to asynchronous read array mode. RST# must be low during power-up. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of CE# or WE# (whichever goes high first). WRITE PROTECT: When WP# is VIL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and lockeddown. When WP# is VIH, lock-down is disabled. WAIT: Outputs data valid status in synchronous burst mode while OE# is asserted. When high (VOH) during a burst mode, data is valid. WAIT# low (V OL) indicates invalid data. WAIT# is pulled high (VOH) by an internal resister. The WAIT# signals of the multiple devices can be tied together to drive one system WAIT# signal. WAIT# is used only for synchronous burst mode. It also works during a continuous burst mode or 4-, 8word burst with no-wrap (RCR.3="1") mode
DQ0-DQ15
INPUT/ OUTPUT
CE#
INPUT
CLK
INPUT
ADV#
INPUT
RST#
INPUT
OE# WE#
INPUT INPUT
WP#
INPUT
WAIT#
OUTPUT
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VPP
INPUT
Table 3.2. Pin Descriptions (Continued) MONITORING POWER SUPPLY VOLTAGE: VPP is not used for power supply pin. With VPP VPPLK, block erase, full chip erase, (page buffer) program or OTP program cannot be executed and should not be attempted. Applying 12V0.3V to VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin. Applying 12V0.3V to VPP during erase/program can only be done for a maximum of 1000 cycles on each block. VPP may be connected to 12V0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits may reduce block cycling capability or cause permanent damage. DEVICE POWER SUPPLY (see specifications): With VCC VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see DC Characteristics) produce spurious results and should not be attempted. INPUT/OUTPUT POWER SUPPLY (see specifications): Power supply for all input/ output pins. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated.
VCC VCCQ GND NC
SUPPLY
SUPPLY SUPPLY
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1.4 Product Description 1.4.1 Memory Block Organization
The device is divided into four physical planes and the partitions can be flexibly configured by the Set Partition Configuration Register command. This allows dual work operations, that is, simultaneous read-while-erase and read-while-program operations. For the address locations of the blocks, see the memory map in Figure 2.1 through Figure 3.2.
1.4.6 OTP (One Time Program) block
The OTP block is a special block that cannot be erased in order to secure the high system reliability. This 8-word (128-bit) OTP block is independent of the 32M-bit or 64M-bit memory area. Figure 4 shows the OTP block address map. The OTP block is divided into two areas. One is a factory programmed area where a unique number has been programmed in SHARP factory. This factory programmed area is "READ ONLY" (already locked). The other is a customer programmable area that can be available for customers. This customer programmable area can also be locked. After locking, this customer programmable area is protected permanently. The data within the OTP block can be read by the Read Identifier Codes/OTP command (90H). To return to read array mode, write the Read Array command (FFH) to the CUI. The OTP block bits are programmed by writing the OTP Program command (C0H) to the CUI. Write the OTP Program command (C0H) at the 1st command cycle and then write the address and the data at the 2nd cycle. If the OTP program operation is failed, the status register bit SR.4 is set to "1". If the OTP block is locked, the status register bits SR.4 and SR.1 are set to "1". The OTP block can be locked using the OTP Program command (C0H). Write the OTP Program command (C0H) at the 1st command cycle and then write the data (FFFDH) to the lock location (80H) at the 2nd cycle. Read cycle from address (80H) indicates the lockout state of the OTP block. Bit 0 of address (80H) means the factory programmed area lock state ("1" is "NOT LOCKED" and "0" is "LOCKED"). Bit 1 of address (80H) means the customer programmable lock state. OTP block lockout state is not reversible. Unlike the main array block lock configuration, the lock state of the OTP block is kept unchanged even if the power is turned off or reset operation is performed. The OTP Program command is only available for programming the OTP block. Page buffer program operations are available for the main array. OTP program cannot be suspended through the (Page Buffer) Program Suspend command (described later). Dual work operation cannot be executed during OTP program.
1.4.2 Four Physical Planes
LH28F320BX/LH28F640BX series has four physical planes (one parameter plane and three uniform planes). Each plane consists of 8M-bit (32M-bit device) or 16Mbit (64M-bit device) Flash memory. The parameter plane consists of eight 4K-word parameter blocks and fifteen (32M-bit device) or thirty-one (64M-bit device) 32Kword main blocks. Each uniform plane consists of sixteen (32M-bit device) or thirty-two (64M-bit device) 32Kword main blocks. Each block can be erased independently up to 100,000 times.
1.4.3 Partition
Partition boundaries can be configured by the Set Partition Configuration Register command. Dual work operation can be done in two partitions. See partition configuration in Table 17 and Figure 17 for more detail. Only one partition can be erased or programmed at a time and burst reads cannot cross partition boundaries. Simultaneous operation modes are shown in Table 2.
1.4.4 Parameter Block
Eight 4K-word parameter blocks within the parameter partition are provided as the memory area to facilitate storage of frequently update small parameters that would normally be stored in EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. The protection of the parameter block is controlled using a combination of the VPP, RST#, WP#, block lock bit and block lock-down bit.
1.4.5 Main Block
32K-word main blocks can store code and/or data. The protection of the main block is also controlled using a combination of the VPP, RST#, WP#, block lock bit and block lock-down bit.
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Figure 2.1. Memory Map for LH28F320BX series (Top Parameter)
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Figure 2.2. Memory Map for LH28F320BX series (Bottom Parameter)
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Figure 3.1. Memory Map for LH28F640BX series (Top Parameter)
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Figure 3.2. Memory Map for LH28F640BX series (Bottom Parameter)
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Figure 4. OTP Block Address Map for OTP Program(1, 2) (The area outside 80H~88H cannot be used.) NOTES: 1. A21 is not used for 32M-bit device. 2. Refer to Table 6 through Table 8 as to the OTP block address map for read operation.
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2 Principles of Operation
Synchronous/Page Mode Dual Work Flash memory LH28F320BX/LH28F640BX series includes an on-chip WSM (Write State Machine) and can automatically execute block erase, full chip erase, (page buffer) program or OTP program operation after writing the proper command to the CUI (Command User Interface).
lock configuration codes, device configuration codes, data within the OTP block and query codes. In any block, the user can store an interface software that initiates and polls progress of block erase or (page buffer) program. Because the LH28F320BX/LH28F640BX series has dual work function, data can be read from the partition not being erased or programmed without using the block erase suspend or (page buffer) program suspend. When the target partition is being erased or programmed, block erase suspend or (page buffer) program suspend allows system software to read/program data from/to blocks other than that which is suspended.
2.1 Operation Mode after Power-up or Reset Mode
After initial power-up or reset mode (refer to Bus Operation in Section 3), the device defaults to the following mode. * Asynchronous read mode in which 8-word page mode is available * Plane 0-2 are merged into one partition for top parameter devices and plane1-3 are merged into one partition for bottom parameter devices. * All blocks default to locked state and are not lockeddown. Manipulation of external memory control pins (CE#, OE#) allow read array, standby and output disable modes.
2.3 Status Register for Each Partition
The LH28F320BX/LH28F640BX series has status registers for each partition. The 8-bit status register is available to monitor the partition state, or the erase or program status. Status Register indicates the status of the partition, not WSM. Even if the status register bit SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. The status register reports if an erase or program operation to each partition has been successfully completed, and if not, indicates a reason for the error. This register cannot be set, only can be cleared by writing the Clear Status Register command or by resetting the device.
2.2 Read, Program and Erase Operation
Independent of the VPP voltage, the memory array, status register, identifier codes, OTP block and query codes can be accessed. And also, set/clear block lock configuration, set read configuration register and set partition configuration register are available even if the VPP voltage is lower than VPPLK. Applying the specified voltage on VCC and VPPH1/2 on VPP enables successful block erase, full chip erase, (page buffer) program and OTP program operation. All functions associated with altering memory contents, which is block erase, full chip erase, (page buffer) program and OTP program, are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. Addresses and data are internally latched on the rising edge of CE# or WE# whichever goes high first during command write cycles. The CUI contents serve as input to the WSM, which controls block erase, full chip erase, (page buffer) program and OTP program. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and margining of data. Writing the appropriate command outputs array data, status register data, identifier codes,
2.4 Data Protection
Block lock bit and block lock-down bit can be set for each block, to protect the data within its block. If the RST# is driven low (VIL), or if the voltage on the VCC pin is below the write lock out voltage (VLKO), or if the voltage on the VPP pin is below the write lock out voltage (VPPLK), then all write functions including OTP program are disabled. The system should be designed to switch the voltage on VPP below the write lock out voltage (VPPLK) for read cycles. This scheme provides the data protection at the hardware level. The two-cycle command sequence architecture for block erase, full chip erase, (page buffer) program, OTP program, and block lock configuration provides the data protection at the software level against data alternation.
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3 Bus Operation
The system CPU reads and writes the flash memory. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Table 4 lists the bus operation.
3.3 Standby
CE# at a logic-high level (VIH) places the LH28F320BX/ LH28F640BX series in standby mode. In standby mode, the LH28F320BX/LH28F640BX series substantially reduces its power consumption because almost of all internal circuits are inactive. DQ0-DQ15 outputs a High Z state independent of OE#. Even if CE# is set to VIH during block erase, full chip erase, (page buffer) program or OTP program, the device continues the operation and consumes active power until the completion of the operation.
3.1 Read Array
LH28F320BX/LH28F640BX series has seven control pins (CLK, CE#, OE#, ADV#, WE#, RST# and WP#). When RST# is VIH, read operations access the memory array, status register, identifier codes, OTP block and query codes independent of the voltage on VPP. The device is automatically initialized upon power-up or device reset mode and set to asynchronous read mode in which 8-word page mode is available. As necessary, write the appropriate read command (Read Array, Read Identifier codes/OTP, Read Query or Read Status Register command) with the partition address to the CUI (Command User Interface). The CUI decodes the partition address and set the target partition to the appropriate read mode. Synchronous burst mode can be set by writing the Set Read Configuration Register command. It is impossible to set one partition to asynchronous read mode and other partition to synchronous burst mode at a time. Asynchronous page mode and synchronous burst mode are available only for main array, that is, parameter blocks and main blocks. Read operations for status register, identifier codes, OTP block and query codes support single asynchronous read cycle or single synchronous read cycle. To read data from the LH28F320BX/LH28F640BX series, RST# and WE# must be at VIH, and CE# and OE# at VIL. ADV# must be driven VIL to fetch address. CE# is the device selection control, and CE#-low enables the selected memory device. OE# is the data output (DQ0DQ15) control and OE#-low drives the selected memory data onto the I/O bus.
3.4 Reset
Driving RST# to logic-low level (VIL) places the LH28F320BX/LH28F640BX series in reset mode. If RST# is held VIL for a minimum tPLPH in read modes, the device is deselected and internal circuitry is turned off. Outputs are placed in a High Z state. Status register is set to 80H. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The device returns to the initial mode described in Section 2.1. During block erase, full chip erase, (page buffer) program or OTP program mode, RST#-low will abort the operation. Memory contents being altered are no longer valid; the data may be partially erased or programmed. Status register bit SR.7 remains "0" until the reset operation has been completed. After RST# goes to VIH, time t PHWL and tPHEL is required before another command can be written. As with any automated device, it is important to assert RST# during system reset. When the system comes out of reset, it expects to read the data from the flash memory. LH28F320BX/LH28F640BX series allows proper CPU initialization following a system reset through the use of the RST# input. In this application, RST# is controlled by the same RESET# signal that resets the system CPU. After return from reset mode, the LH28F320BX/ LH28F640BX series is automatically set to asynchronous read mode in which 8-word page mode is available. Delay time tPHQV is required until memory access outputs are valid.
3.2 Output Disable
With OE# at VIH, the device outputs are disabled. Output pins DQ0 - DQ15 are placed in a high-impedance (High Z) state.
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Table 4. Bus Operation (1, 2) Mode Read Array Output Disable Standby Reset 3 Notes RST# 6 VIH VIH VIH VIL VIH CE# VIL VIL VIH X OE# VIL VIH X X WE# VIH VIH X X Address X X X X See Table 6 through Table 8 See Section 6 X VPP X X X X DQ0-15 DOUT High Z High Z High Z See Table 6 through Table 8 See Section 6 DIN
Read Identifier Codes/OTP
6
VIL
VIL
VIH
X
Read Query Write
6,7 4,5,6
VIH VIH
VIL VIL
VIL VIH
VIH VIL
X X
NOTES: 1. Refer to DC Characteristics. When VPP VPPLK, memory contents can be read, but cannot be altered. 2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and VPPH1/2 voltages. 3. RST# at GND0.2V ensures the lowest power consumption. 4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when VPP=VPPH1/2 and VCC is the specified voltage. 5. Refer to Table 5 for valid DIN during a write operation. 6. Never hold OE# low and WE# low at the same timing. 7. Refer to Appendix of LH28F320BX/LH28F640BX series for more information about query code.
3.5 Read Identifier Codes/OTP
The manufacturer code, device code, block lock configuration codes, read configuration register code, partition configuration register code and the data within the OTP block can be read in the read identifier codes/ OTP mode (see Table 6 through Table 8). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms.
Query command. The CFI data structure contains information such as block size, density, command set and electrical specifications (see Section 6). In this mode, read cycles retrieve CFI information. To return to read array mode, write the Read Array command (FFH) with the partition address.
3.7 Write the Command to the CUI
Except for the Full Chip Erase command, writing commands to the CUI always requires the word address, block address or partition address. Before writing the Block Erase command, Full Chip Erase command, (Page Buffer) Program command or OTP Program command, WSM (Write State Machine) should be ready and not be used in any partition.
3.6 Read Query
CFI (Common Flash Interface) code, which is called query code, can be read after writing the Read Query command. The address to read query code should be in the partition address which is written with the Read
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Applying the specified voltage on VCC and VPPH1/2 on VPP enables successful block erase, full chip erase, (page buffer) program or OTP program with writing the proper command and address to the CUI. Erase or program operation may occur in only one partition at a time. Other partitions must be in one of the read modes. The Block Erase command requires appropriate command and an address within the block to be erased. The Full Chip Erase command requires appropriate command. The (Page Buffer) Program command requires appropriate command and an address of the location to be programmed. The Set/Clear Block Lock Bit or Set Block Lock-down Bit command requires appropriate command and an address within the target block. The OTP Program command requires appropriate command and an address of the location to be programmed within the OTP block. The Set Read Configuration Register command or the Set Partition Configuration Register command requires appropriate command and configuration register code presented on the addresses A0-A15. The CUI itself does not occupy an addressable memory location. When both CE# and WE# go VIL (valid), the command is written to CUI and the address and data are latched on the rising edge of CE# or WE#, whichever goes high first. The command can be written to the CUI at the standard microprocessor writing timing.
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4 Command Definitions
Operations of the device are selected by the specific commands written to the CUI (Command User Interface). Since commands are partition-specific, it is important to write commands within the target partition's address range (see Table 5). Each command except for the Full Chip Erase command and OTP Program command affects only the mode of the partition to which the command is written.
4.2 Read Identifier Codes/OTP Command
The read identifier codes/OTP mode is initiated by writing the Read Identifier Codes/OTP command (90H) to the target partition. Read operations to that partition output the identifier codes or the data within the OTP block. To terminate the operation, write another valid command to the partition. In this mode, the manufacturer code, device code, block lock configuration codes, read configuration register code, partition configuration register code and the data within the OTP block as well as the OTP block lock state can be read on the addresses shown in Table 6 through Table 8. Once the internal WSM has started block erase, full chip erase, (page buffer) program or OTP program in one partition, the partition will not recognize the Read Identifier Codes/ OTP command until the WSM completes its operation or unless the WSM is suspended via the Block Erase Suspend or (Page Buffer) Program Suspend command. However, the Read Identifier Codes/OTP command can be accepted in other partitions except for full chip erase or OTP program operation. Like the Read Array command, the Read Identifier Codes/OTP command functions independently of the VPP voltage and RST# must be at VIH. To read the data in the OTP block, it is important to write addresses within the OTP area's address range (refer to Table 6 through Table 8). Asynchronous page mode and synchronous burst mode are not available for reading identifier codes/OTP. Read operations for identifier codes or OTP block support single asynchronous read cycle or single synchronous read cycle.
4.1 Read Array Command
Upon initial device power-up or after reset mode, all the partitions in the device default to asynchronous read mode in which 8-word page mode is available. The Read Array command to a partition places the partition to read array mode. The partition remains enabled for read array mode until another valid command is written to the partition. When RST# is at VIH, the Read Array command is valid independent of the voltage on VPP. Once the internal WSM (Write State Machine) has started block erase, full chip erase, (page buffer) program or OTP program in one partition, the partition will not recognize the Read Array command until the WSM completes its operation or unless the WSM is suspended via the Block Erase Suspend or (Page Buffer) Program Suspend command. However, the Read Array command can be accepted in other partitions except for full chip erase or OTP program operation. Since LH28F320BX/LH28F640BX series provide dual work capability, partitions not executing block erase or (page buffer) program operation are allowed to set to the read array mode and the memory array data within the partitions can be read without suspending block erase or (page buffer) program operation.
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Table 5. Command Definitions(11) Command Bus Cycles Req'd 1 2 2 2 1 2 2 2 4 1 1 2 2 2 2 2 2 Notes Oper(1) 2 2,3,4 2,3,4 2,3 2 2,3,5 2,5,9 2,3,5,6 2,3,5,7 2,8,9 2,8,9 2 2,10 2 2,3,9 2,3 2,3 Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write First Bus Cycle Addr(2) PA PA PA PA PA BA X WA WA PA PA BA BA BA OA RCRC PCRC Data(3) FFH 90H 98H 70H 50H 20H 30H 40H or 10H E8H B0H D0H 60H 60H 60H C0H 60H 60H Write Write Write Write Write Write BA BA BA OA RCRC PCRC Write Write Write Write BA X WA WA Read Read Read IA or OA QA PA Second Bus Cycle Oper(1) Addr(2)
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Data(3)
Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume Set Block Lock Bit Clear Block Lock Bit Set Block Lock-down Bit OTP Program Set Read Configuration Register Set Partition Configuration Register
ID or OD QD SRD D0H D0H WD N-1
01H D0H 2FH OD 03H 04H
NOTES: 1. Bus operations are defined in Table 4. 2. First bus cycle command address should be the same as the second cycle address. X=Any valid address within the device. PA=Address within the selected partition. IA=Identifier codes address (See Table 6 through Table 8). QA=Query codes address. Refer to Appendix of LH28F320BX/LH28F640BX series for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. OA=Address of OTP block to be read or programmed (See Figure 4). RCRC=Read configuration register code presented on the addresses A0-A15. PCRC=Partition configuration register code presented on the address A0-A15. 3. ID=Data read from identifier codes. (See Table 6 through Table 8). QD=Data read from query database. Refer to Appendix of LH28F320BX/LH28F640BX series for details. SRD=Data read from status register. See Table 9 for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). OD=Data to be programmed at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, read configuration register code, partition configuration register code and the data within OTP block (See Table 6 through Table 8). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST# is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
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7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target partition to be programmed and the confirm command (D0H). Refer to Appendix of LH28F320BX/LH28F640BX series for details. 8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while the block erase operation is being suspended. 10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP# is VIL. When WP# is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
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Table 6. Identifier Codes and OTP Address for Read Operation Code Manufacturer Code Device Code (32M-bit device) Device Code (64M-bit device) Block Code Lock Manufacturer Code 32M Top Parameter Device Code 32M Bottom Parameter Device Code 64M Top Parameter Device Code 64M Bottom Parameter Device Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code OTP Read Configuration Register Partition Configuration Register OTP Lock OTP 0005H 0006H 0080H 0081-0088H Address [A15-A0](1) 0000H 0001H 0001H 0001H 0001H Block Address +2 Data [DQ15-DQ0] 00B0H 00B4H 00B5H 00B0H 00B1H DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 RCRC PCRC OTP-LK OTP 2 3 2 3 4 4 4 4 5 6 7 8 Notes
Configuration Block is Unlocked
NOTES: 1. The address A20-A16 to read the manufacturer, device, lock configuration, device configuration code and OTP data are shown in below table. 2. Top parameter device has its parameter blocks in the plane3 (The highest address). 3. Bottom parameter device has its parameter blocks in the plane0 (The lowest address) 4. DQ15-DQ2 is reserved for future implementation. 5. RCRC=Read Configuration Register Code. 6. PCRC=Partition Configuration Register Code. 7. OTP-LK=OTP Block Lock configuration. 8. OTP=OTP Block data.
Table 7. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) for 32M-bit device Partition Configuration Register PCR.10 0 0 0 1 0 1 1 1 PCR.9 0 0 1 0 1 1 0 1 PCR.8 0 1 0 0 1 0 1 1 00H 00H or 08H 00H or 10H 00H or 18H 00H or 08H or 10H 00H or 10H or 18H 00H or 08H or 18H 00H or 08H or 10H or 18H Address (32M-bit device) [A20-A16]
NOTES: 1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read Identifier Codes/OTP command (90H).
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Table 8. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) for 64M-bit device Partition Configuration Register PCR.10 0 0 0 1 0 1 1 1 PCR.9 0 0 1 0 1 1 0 1 PCR.8 0 1 0 0 1 0 1 1 00H 00H or 10H 00H or 20H 00H or 30H 00H or 10H or 20H 00H or 20H or 30H 00H or 10H or 30H 00H or 10H or 20H or 30H Address (64M-bit device) [A21-A16]
NOTES: 1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read Identifier Codes/OTP command (90H).
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4.3 Read Query Command
The read query mode is initiated by writing the Read Query command (98H) to the target partition. Read operations to that partition output the query code (Common Flash Interface code) shown in Section 6. To terminate the operation, write another valid command to the partition. Once the internal WSM has started block erase, full chip erase, (page buffer) program or OTP program in one partition, the partition will not recognize the Read Query command until the WSM completes its operation or unless the WSM is suspended via the Block Erase Suspend or (Page Buffer) Program Suspend command. However, the Read Query command can be accepted in other partitions except for full chip erase or OTP program operation. Like the Read Array command, the Read Query command functions independently of the VPP voltage and RST# must be at VIH. Refer to Section 6 for more information about query code. Asynchronous page mode and synchronous burst mode are not available for reading query code. Read operations for query code support single asynchronous read cycle or single synchronous read cycle.
Asynchronous page mode and synchronous burst mode are not available for reading status register. Read operations for status register support single asynchronous read cycle or single synchronous read cycle. During the dual work operation, the status register data is read from the partition which is executing block erase or (page buffer) program operation. The memory array data can be read from other partitions which are not executing block erase or (page buffer) program operation. The partition to be accessed is automatically identified according to the input address.
4.5 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 and SR.1 that have been set to "1"s by the WSM can only be cleared by writing the Clear Status Register command (50H). This command functions independently of the VPP voltage. RST# must be at VIH. To clear the status register, write the Clear Status Register command and an address within the target partition to the CUI. Status register bits SR.5, SR.4, SR.3 and SR.1 indicate various error conditions occurring after writing commands (see Table 9). When erasing multiple blocks or programming several words in sequence, clear these bits before starting each operation. The status register bits indicate an error for during the sequence. After executing the Clear Status Register command, the partition returns to read array mode. This command clears only the status register of the addressed partition. During block erase suspend or (page buffer) program suspend, the Clear Status Register command is invalid and the status register cannot be cleared.
4.4 Read Status Register Command
The status register may be read to determine when block erase, full chip erase, (page buffer) program or OTP program has been completed and whether the operation has been successfully completed or not (see Table 9). The status register can be read at any time by writing the Read Status Register command (70H) to the target partition. Subsequent read operations to that partition output the status register data until another valid command is written. The status register contents are latched on the falling edge of OE# or CE# whichever occurs later. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage and RST# must be at VIH.
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Table 9. Status Register Definition R 15 WSMS 7 R 14 BESS 6 R 13 BEFCES 5 R 12 PBPOPS 4 R 11 VPPS 3 R 10 PBPSS 2 NOTES: R 9 DPS 1 R 8 R 0
SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) * 1 = Ready * 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) * 1 = Block Erase Suspended * 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) * 1 = Error in Block Erase or Full Chip Erase * 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM STATUS (PBPOPS) * 1 = Error in (Page Buffer) Program or OTP Program * 0 = Successful (Page Buffer) Program or OTP Program SR.3 = VPP STATUS (VPPS) * 1 = VPP LOW Detect, Operation Abort * 0 = VPP OK SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) * 1 = (Page Buffer) Program Suspended * 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) * 1 = Erase or Program Attempted on a Locked Block, Operation Abort * 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. Check SR.7 to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.0 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit or set read/partition configuration register attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. SR.3 is not guaranteed to report accurate feedback when VPP VPPH1, VPPH2 or VPPLK. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status. SR.15 - SR.8 and SR.0 are reserved for future use and should be masked out when polling the status register.
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Table 10. Extended Status Register Definition R 15 SMS 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 R 10 R 2 R 9 R 1 R 8 R 0
XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) * 1 = Page Buffer Program available * 0 = Page Buffer Program not available
NOTES: After issue a Page Buffer Program command (E8H), XSR.7=1 indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) should be masked out when polling the extended status register.
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4.6 Block Erase Command
The two-cycle Block Erase command initiates one block erase at the addressed block within the target partition. Read operations to that partition output the status register data of its partition. At the first cycle, command (20H) and an address within the block to be erased is written to the CUI, and command (D0H) and the same address as the first cycle is written at the second cycle. Once the Block Erase command is successfully written, the WSM automatically starts erase and verification processes. The data in the selected block are erased (becomes FFFFH). The system CPU can detect the block erase completion by analyzing the output data of the status register bit SR.7. The partition including the block to be erased remains in read status register mode after the completion of the block erase operation until another command is written to the CUI. Figure 5.1 and Figure 5.2 show a flowchart of the block erase operation. Check the status register bit SR.5 at the end of block erase. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The partition remains in read status register mode until a new command is written to that partition. This two-cycle command sequence ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in status register bits SR.5 and SR.4 of the partition being set to "1" and the operation will be aborted. For reliable block erase operation, apply the specified voltage on VCC and VPPH1/2 on VPP. In the absence of this voltage, block erase operations are not guaranteed. For example, attempting a block erase at VPP VPPLK causes SR.5 and SR.3 being set to "1". Also, successful block erase requires that the selected block is unlocked. When block erase is attempted to the locked block, bits SR.5 and SR.1 will be set to "1". Block erase operation may occur in only one partition at a time. Other partitions must be in one of the read modes.
outputs the status register data when any address within the device is selected. The WSM automatically starts the erase operation for all unlocked blocks, skipping the locked blocks. The full chip erase operation cannot be suspended through the erase suspend command (described later). The system CPU can detect the full chip erase completion by analyzing the output data of the status register bit SR.7. All the partitions remain in the read status register mode after the completion of the full chip erase operation until another command is written to the CUI. Figure 6.1 and Figure 6.2 show a flowchart of the full chip erase operation. The WSM aborts the operation upon encountering an error during the full chip erase operation and leaves the remaining blocks not erased. After the full chip erase operation, check the status register bit SR.5. When a full chip erase error is detected, SR5 of all partitions will be set to "1". The status registers for all partitions should be cleared before system software attempts corrective actions. After that, retry the Full Chip Erase command or erase block by block using the Block Erase command. This two-cycle command sequence ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in status register bits SR.5 and SR.4 of all partitions being set to "1" and the operation will be aborted. For reliable full chip erase operation, apply the specified voltage on VCC and VPPH1/2 on VPP. In the absence of this voltage, full chip erase operations are not guaranteed. For example, attempting a full chip erase at VPP VPPLK causes SR.5 and SR.3 being set to "1". As previously mentioned, the Full Chip Erase command erases all blocks except for the locked blocks. Unlike the block erase, the status register bits SR.5 and SR.1 are not set to "1" even if the locked block is included. However, when all blocks are locked, the bits SR.5 and SR.1 are set to "1" and the operation will not be executed. If an error is detected during the full chip erase operation, error bits for all status registers are set to "1". This requires that the Clear Status Register command be written to all partitions to clear the error bits. Dual work operation is not available during the full chip erase mode. The memory array data cannot be read in this mode. To return to the read array mode, write the Read Array command (FFH) to the CUI after the completion of the full chip erase operation.
4.7 Full Chip Erase Command
The two-cycle Full Chip Erase command erases all of the unlocked blocks. Before writing this command, all of the partitions should be ready (WSM should not be occupied by any partition). At the first cycle, command (30H) is written to the CUI, and command (D0H) is written at the second cycle. After writing the command, the device
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Bus Operation
Command
Comments Data=20H Addr=Within Block to be Erased Data=D0H Addr=Within Block to be Erased Status Register Data Addr=Within Block to be Erased Check SR.7 1=WSM Ready 0=WSM Busy
Write
Block Erase
Read
Standby
When subsequently erasing a block, repeat the above sequence. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after a sequence of block erasures to place device in read array mode.
Bus Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.6 1=Block Erase Suspended 0=Block Erase Completed Check SR.2 1=(Page Buffer) Program Suspended 0=(Page Buffer) Program Completed
Standby
Standby
Standby
Figure 5.1. Automated Block Erase Flowchart
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Bus Operation Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Block lock bit is set. Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1=Block Erase Error
Standby
Standby
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Figure 5.2. Automated Block Erase Flowchart (Continued)
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Bus Operation
Command
Comments Data=30H Addr=X Data=D0H Addr=X Status Register Data Addr=X Check SR.7 1=WSM Ready 0=WSM Busy
Write
Full Chip Erase
Read
Standby
Check the status after full chip erase. Write FFH after the full chip erase to place device in read array mode.
Bus Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.6 1=Block Erase Suspended 0=Block Erase Completed Check SR.2 1=(Page Buffer) Program Suspended 0=(Page Buffer) Program Completed
Standby
Standby
Standby
Figure 6.1. Automated Full Chip Erase Flowchart
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Bus Operation Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect All Blocks are locked. Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1=Full Chip Erase Error
Standby
Standby
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Figure 6.2. Automated Full Chip Erase Flowchart (Continued)
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4.8 Program Command
A two-cycle command sequence written to the target partition initiates a word program operation. Read operations to the target partition to be programmed output the status register data until another valid command is written. At the first cycle, write command (standard 40H or alternate 10H) and an address of memory location to be programmed, followed by the second write that specifies the address and data. The WSM then takes over, controlling the internal word program algorithm. The system CPU can detect the word program completion by analyzing the output data of the status register bit SR.7. Figure 7.1 and Figure 7.2 show a program flowchart. The internal WSM verify only detects errors for "1"s that are not successfully programmed to "0"s. Check the status register bit SR.4 at the end of word program. If a word program error is detected, the status register should be cleared before system software attempts corrective actions. The partition remains in read status register mode until it receives another command. For reliable word program operation, apply the specified voltage on VCC and VPPH1/2 on VPP. In the absence of this voltage, word program operations are not guaranteed. For example, attempting a word program at VPP VPPLK causes SR.4 and SR.3 being set to "1". Also, successful word program requires for the selected block is unlocked. When word program is attempted to the locked block, bits SR.4 and SR.1 will be set to "1". Word program operation may occur in only one partition at a time. Other partitions must be in one of the read modes.
4.9 Page Buffer Program Command
The LH28F320BX/LH28F640BX series has two planes of 16-word page buffer, which can perform fast sequential programming up to 32 words. The data are once loaded to the page buffer and programmed to the flash array when the confirm command (D0H) is written. See the flowchart in Figure 8.1 and Figure 8.2. The page buffer program is executed by at least fourcycle or up to 19-cycle command sequence. First, write the Page Buffer Program setup command (E8H) and start address to the partition's CUI. At this point, read operations to the target partition to be programmed output the extended status register data (see Table 10). Check the extended status register data. If the extended status register bit XSR 7 is "0", no page buffer is available and Page Buffer Program setup command which has just been written is ignored. To retry, continue monitoring XSR.7 by writing Page Buffer Program setup (E8H) with program address until XSR.7 transitions to "1". When XSR.7 transitions to "1", the setup command written is valid. Then, at the second cycle, write the word count [N]-1 and start address if the number of words to be programmed is [N] in total. That is, when the number of [N] is 1 word, write (00H); if [N] is 16 words, write (0FH). The word count [N]-1 must be less than or equal to 0FH. Attempting to write more than 0FH for the word count causes the sequence error and the status register bits SR.5 and SR.4 are set to "1". After writing a word count [N]-1, read operations to the target partition to be programmed output the status register data. At the third cycle following the write of [N]-1, write the first data to be programmed and start address to the partition's CUI. Lower 4 bits (A0-A3) of the start address also correspond to the page buffer address and the data are stored in the page buffer. At the fourth and subsequent cycles, write additional data and address, depending on the count. All subsequent address must lie within the start address plus the count. After writing the Nth word data, write the confirm command (D0H) and an address within the target partition at the last cycle. This initiates the WSM to being transferring the data from the page buffer to the flash array. If a command other than the confirm command (D0H) is written, sequence error occurs and status register bits SR.5 and SR.4 of the partition are set to "1". When the data are transferred from the page buffer to the flash array, the status register bit SR.7 is set to "0". Then, the target partition is in the page buffer program busy mode.
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For additional page buffer program, write another Page Buffer Program setup command (E8H) and check XSR.7. The Page Buffer Program command can be queued while WSM is busy as long as XSR.7 indicates "1", because LH28F320BX/LH28F640BX series has two buffers. If an error occurs while programming, the device will stop programming and flush next page buffer program command which has been previously queued. Status register bit SR.4 is set to "1". SR.4 should be cleared before writing next command. If the Page Buffer Program command is attempted past an erase block boundary, the device will program the data to the flash array up to an erase block boundary and then stop programming. The status register bits SR.5 and SR.4 will be set to "1" (command sequence error). SR.5 and SR.4 should be cleared before writing next command. For reliable page buffer program operation, apply the specified voltage on VCC and VPPH1/2 on VPP. In the absence of this voltage, page buffer program operations are not guaranteed. For example, attempting a page buffer program at VPP VPPLK causes SR.4 and SR.3 being set to "1". Also, successful page buffer program requires for the selected block is unlocked. When page buffer program is attempted to the locked block, bits SR.4 and SR.1 will be set to "1". During page buffer program, dual work operation is available. The array data can be read from partitions not being programmed. Page buffer program operation may occur in only one partition at a time. Other partitions must be in one of the read modes.
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Bus Operation
Command
Comments Data=40H or 10H Addr=Location to be Programmed Data= Data to be Programmed Addr=Location to be Programmed Status Register Data Addr=Location to be Programmed Check SR.7 1=WSM Ready 0=WSM Busy
Write
Word Program
Read
Standby
Repeat the above sequence for the subsequent word programs. SR full status check can be done after each word program, or after a sequence of word programs. Write FFH after a sequence of word programs to place device in read array mode.
Bus Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.2 1=Program Suspended 0=Program Completed
Standby
Standby
Figure 7.1. Automated Program Flowchart
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Bus Operation Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Block lock bit is set. Check SR.4 1=Word Program Error
Standby
Standby
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Figure 7.2. Automated Program Flowchart (Continued)
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Bus Operation Write
Command
Comments
Page Buffer Data=E8H Program Addr=Start Address Extended Status Register Data Check XSR.7 1=Page Buffer Program Ready 0=Page Buffer Program Busy Data=[Word Count N]-1 Addr=Start Address Data=Buffer Data Addr=Start Address
Read
Standby
Write (Note 1) Write (Note 2, 3)
Page Buffer <(N+2)th cycle> Program Data=Buffer Data Write Addr=Sequential Address (Note 4, 5) following start address Write <(N+3)th cycle> Data=D0H Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
Read
Standby
1. Word count values on DQ0-7 are loaded into count register. 2. Write Buffer contents will be programmed at the start address. 3. Align the start address on a Write Buffer boundary for maximum programming performance. 4. The device aborts the Page Buffer Program command if the current address is outside of the original block address. 5. The Status Register indicates an "improper command sequence" if the Page Buffer Program command is aborted. Follow this with a Clear Status Register command. SR full status check can be done after each page buffer program, or after a sequence of page buffer programs. Write FFH after the last page buffer program operation to place device in read array mode.
Figure 8.1. Automated Page Buffer Program Flowchart
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Bus Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.2 1=Program Suspended 0=Program Completed
Standby
Standby
Bus Operation Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Block lock bit is set. Check SR.4,5 Both 1=Command Sequence Error Check SR.4 1=Page Buffer Program Error
Standby
Standby
Standby
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the Status Register before attempting retry or other error recovery.
Figure 8.2. Automated Page Buffer Program Flowchart (Continued)
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4.10 Block Erase Suspend Command and Block Erase Resume Command
The Block Erase Suspend command (B0H) allows block erase interruption to read or program data in the blocks other than that which is suspended. This command is valid for the block erase operation and the full chip erase operation can not be suspended. Once the block erase process starts in a partition, writing the Block Erase Suspend command to the partition requests that the WSM suspends the block erase sequence at a predetermined point in the algorithm. Read operations to the target partition after writing the Block Erase Suspend command access the status register. Status register bits SR.7 and SR.6 indicate if the block erase operation has been suspended (both will be set to "1"). Specification t WHRH2 or tEHRH2 defines the block erase suspend latency. When the Block Erase Suspend command is written after the completion of the block erase operation, the partition returns to read array mode. Therefore, the Read Status Register command (70H) must be written to the target partition after writing the Block Erase Suspend command. If the status register bits SR.7 and SR.6 are set to "1", block erase has been suspended. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A (Page Buffer) Program command sequence can also be written during block erase suspend to program data in other blocks. Using the (Page Buffer) Program Suspend command (see Section 4.11), a program operation can also be suspended during a block erase suspend. During a word program operation with block erase suspended, status register bit SR.7 will return to "0". However, SR.6 will remain "1" to indicate the block erase suspend status. If the Page Buffer Program setup command (E8H) is written to the target partition during block erase suspend in which SR.7 and SR.6 are set to "1", read operations to the target partition to be programmed output the extended status register data. In read extended status register mode, bit XSR.7 is only valid, which indicates that the written command (E8H) is available, and other bits (from XSR.6 to XSR.0) are invalid (see Table 10). When writing the word count [N]-1 and start address at next command cycle, the target partition returns to read status register mode and the status register bits SR.7 and SR.6 are set to "1". After the Page Buffer Program confirm command (D0H) is written, the status register bit SR.7 will return to
"0". However, SR.6 will remain "1" to indicate the block erase suspend status. The only other valid commands while block erase is suspended are Read Identifier Codes/OTP, Read Query, Read Status Register, Set Block Lock Bit, Clear Block Lock Bit, Set Block Lock-down Bit, Set Read Configuration Register and Block Erase Resume command. To resume the block erase operation, write the Block Erase Resume command (D0H) to the partition. Status Register bits SR.7 and SR.6 will be automatically cleared. After the Block Erase Resume command is written, the target partition automatically outputs the status register data when read. VPP must remain at VPPH1/2 (at the same level before block erase suspended) while block erase is suspended. RST# must remain at VIH and WP# must also remain at VIL or VIH (at the same level before block erase suspended). Block erase cannot resume until (page buffer) program operation initiated during block erase suspend is completed. Figure 9 shows the block erase suspend and block erase resume flowchart. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished.
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Bus Operation Write Write Read
Command
Comments
Block Erase Data=B0H Suspend Addr=Within Partition Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.6 1=Block Erase Suspended 0=Block Erase Completed Data=D0H Block Erase Addr=Within Block to be Resume Suspended
Standby
Standby
Write
Figure 9. Block Erase Suspend and Block Erase Resume Flowchart
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4.11 (Page Buffer) Program Suspend Command and (Page Buffer) Program Resume Command
The (Page Buffer) Program Suspend command (B0H) allows word and page buffer program interruption to read data from locations other than that which is suspended. Once the (page buffer) program process starts in a partition, writing the (Page Buffer) Program Suspend command to the partition requests that the WSM suspends the (page buffer) program sequence at a predetermined point in the algorithm. Read operations to the target partition after writing the (Page Buffer) Program Suspend command access the status register. Status register bits SR.7 and SR.2 indicate if the (page buffer) program operation has been suspended (both will be set to "1"). Specification tWHRH1 or t EHRH1 defines the (page buffer) program suspend latency. When the (Page Buffer) Program Suspend command is written after the completion of the (page buffer) program operation, the partition returns to read array mode. Therefore, the Read Status Register command (70H) must be written to the target partition after writing the (Page Buffer) Program Suspend command. If the status register bits SR.7 and SR.2 are set to "1", (page buffer) program has been suspended. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while (page buffer) program is suspended are Read Identifier Codes/OTP, Read Query, Read Status Register, Set Read Configuration Register and (Page Buffer) Program Resume command. To resume the (page buffer) program operation, write the (Page Buffer) Program Resume command (D0H) to the partition. Status Register bits SR.7 and SR.2 will be automatically cleared. After the (Page Buffer) Program Resume command is written, the target partition automatically outputs the status register data when read. VPP must remain at VPPH1/2 (at the same level before (page buffer) program suspended) while (page buffer) program is suspended. RST# must remain at VIH and WP# must also remain at VIL or VIH (at the same level before (page buffer) program suspended). Figure 10 shows the (page buffer) program suspend and (page buffer) program resume flowchart.
If the interval time from a (Page Buffer) Program Resume command to a subsequent (Page Buffer) Program Suspend command is short and its sequence is repeated, the (page buffer) program operation may not be finished. After the (Page Buffer) Program Suspend command is written to the 1st partition to suspend the program operation while the 2nd partition is in block erase suspend mode, the (Page Buffer) Program Resume command should be written to the 1st partition first to resume the suspended (page buffer) program operation. After that, the Block Erase Resume command is written to the 2nd partition to resume the suspended block erase operation. If the Block Erase Resume command is written before the (Page Buffer) Program Resume command, the Block Erase Resume command is ignored and the partition to which the Block Erase Resume command is written is set to read array mode with block erase suspended.
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Bus Operation Write
Command
Comments
(Page Buffer) Data=B0H Program Addr=Within Partition Suspend Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.2 1=(Page Buffer) Program Suspended 0=(Page Buffer) Program Completed Data=FFH Addr=Within Partition Read array locations from block other than that being programmed (Page Buffer) Data=D0H Addr=Location to be Program Suspended Resume
Write Read
Standby
Standby
Write
Read
Write
Figure 10. (Page Buffer) Program Suspend and (Page Buffer) Program Resume Flowchart
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4.12 Set Block Lock Bit Command
The LH28F320BX/LH28F640BX series is provided with a block lock bit for each parameter block and main block. The features of set block lock bit is as follows: * Any block can be independently locked by setting its block lock bit. * The time required for block locking is less than the minimum command cycle time (minimum time from the rising edge of CE# or WE# to write the command to the next rising edge of CE# or WE#). * Block erase, full chip erase or (page buffer) program on a locked block cannot be executed (see Table 11 and Table 12). * At power-up or device reset, all blocks default to locked state, regardless of the states before power-off or reset operation. (Lock bit is volatile.) The Set Block Lock Bit command is a two-cycle command. At the first cycle, command (60H) and an address within the block to be locked is written to the target partition. At the second cycle, command (01H) and the same address as the first cycle is written. Read operations to the target partition output the status register
data until another valid command is written. After writing the second cycle command, the block lock bit is set within the minimum command cycle time and the corresponding block is locked. To check the lock status, write the Read Identifier Codes/OTP command (90H) and an address within the target block. Subsequent reads at Block Base Address +2 (see Table 6 through Table 8) will output the lock/unlock status of that block. The lock/unlock status is represented by the output pin DQ0. If the output of DQ0 is "1", the block lock bit is set correctly. Figure 11 shows set block lock bit flowchart. The two-cycle command sequence ensures that block is not accidentally locked. An invalid Set Block Lock Bit command sequence will result in both status register bits SR.5 and SR.4 being set to "1" and the operation will not be executed. The Set Block Lock Bit command is available when the power supply voltage is specified level, independent of the voltage on VPP. At power-up or device reset, since all blocks default to locked state, write the Clear Block Lock Bit command described later to clear block lock bit before a erase or program operation.
Table 11. Functions of Block Lock(1) and Block Lock-Down Current State State [000] [001](4) [011] [100] [101](4) [110](5) [111] WP# 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1
(2)
DQ0(2) 0 1 1 0 1 0 1
State Name Unlocked Locked Locked-down Unlocked Locked Lock-down Disable Lock-down Disable
Erase/Program Allowed? (3) Yes No No Yes No Yes No
NOTES: 1. OTP (One Time Program) block has the lock function which is different from those described above. 2. DQ0=1: a block is locked; DQ0=0: a block is unlocked. DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down. 3. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 4. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation. 5. When WP# is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked.
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Table 12. Block Locking State Transitions upon Command Write(4) Current State State [000] [001] [011] [100] [101] [110] [111] WP# 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 Result after Lock Command Written (Next State) Set Lock(1) [001] No Change(3) No Change [101] No Change [111] No Change Clear Lock(1) No Change [000] No Change No Change [100] No Change [110] Set Lock-down(1) [011](2) [011] No Change [111](2) [111] [111](2) No Change
NOTES: 1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written. 4. In this state transitions table, assumes that WP# is not changed and fixed V IL or VIH.
Table 13. Block Locking State Transitions upon WP# Transition(4) Current State Previous State State [110](2) Other than [110](2) [000] [001] [011] [100] [101] [110] [111] WP# 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 Result after WP# Transition (Next State) WP#=0 1(1) [100] [101] [110] [111] WP#=1 0(1) [000] [001] [011](3) [011]
NOTES: 1. "WP#=0 1" means that WP# is driven to VIH and "WP#=1 0" means that WP# is driven to VIL 2. State transition from the current state [011] to the next state depends on the previous state. 3. When WP# is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.
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Bus Operation
Command
Comments Data=60H Addr=Within Block to be Locked or Locked-down
Write
Set Block Lock Bit/Set Block Lock- down Bit Data= 01H (Lock Bit), or 2FH(Lock-down Bit) Addr=Within Block to be Locked or Locked-down Status Register Data Addr=Within Partition Check SR.4, 5 Both 1=Command Sequence Error Read ID Code Data=90H Addr=Within Partition Lock Bit or Lock-down Bit Data Addr=Block Address+2 (see Table 6 through Table 8) Check DQ0/DQ1 1=Lock Bit or Lock-down Bit is Set
Read
Standby
Write
Read
Standby
Repeat for the subsequent set block lock/lock-down bit. Lock status check can be done after each set block lock/ lock-down bit operation or after a sequence of set block lock/lock-down bit operations. SR.5 and SR.4 are only cleared by the Clear Status Register command in cases where multiple block lock/ lock-down bits are set before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Write FFH after a sequence of set block lock/lock-down bit operations to place device in read array mode.
Bus Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
Standby
Figure 11. Set Block Lock Bit and Set Block Lock-down Bit Flowchart
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4.13 Clear Block Lock Bit Command
A locked block can be unlocked by writing the Clear Block Lock Bit command. The features of clear block lock bit is as follows: * Any block can be independently unlocked by clearing its block lock bit. * The time required to be unlocked is less than the minimum command cycle time (minimum time from the rising edge of CE# or WE# to write the command to the next rising edge of CE# or WE#). * Block erase, full chip erase or (page buffer) program on an unlocked block can be executed (see Table 11 and Table 12). The Clear Block Lock Bit command is a two-cycle command. At the first cycle, command (60H) and an address within the block to be unlocked is written to the target partition. At the second cycle, command (D0H) and the same address as the first cycle is written. Read operations to the target partition output the status register data until another valid command is written. After writing the second cycle command, the block lock bit is cleared within the minimum command cycle time and the corresponding block is unlocked. To check the unlock status, write the Read Identifier Codes/OTP command (90H) and an address within the target block. Subsequent reads at Block Base Address +2 (see Table 6 through Table 8) will output the lock/unlock status of that block. The lock/unlock status is represented by the output pin DQ0. If the output of DQ0 is "0", the block lock bit is cleared correctly. Figure 12 shows clear block lock bit flowchart. The two-cycle command sequence ensures that block is not accidentally unlocked. An invalid Clear Block Lock Bit command sequence will result in both status register bits SR.5 and SR.4 being set to "1" and the operation will not be executed. The Clear Block Lock Bit command is available when the power supply voltage is specified level, independent of the voltage on VPP.
4.14 Set Block Lock-Down Bit Command
The block lock-down bit, when set, increases the security for data protection. The block lock-down bit has the following functions. * Any block can be independently locked-down by setting its block lock-down bit. * The time required to be locked-down is less than the minimum command cycle time (minimum time from the rising edge of CE# or WE# to write the command to the next rising edge of CE# or WE#). * Locked-down block is automatically locked regardless of WP# at VIL or VIH. * When WP# is VIL, locked-down blocks are protected from lock status changes. * When WP# is VIH, the lock-down bits are disabled and locked-down blocks can be individually unlocked by software command. These blocks can then be re-locked and unlocked as desired while WP# remains VIH. When WP# goes VIL, blocks that were previously marked lock-down return to the lock-down state regardless of any changes made while WP# was VIH (see Table 13). * At power-up or device reset, all blocks are not lockeddown regardless of the states before power-off or reset operation. (Lock-down bit is volatile.) * Lock-down bit cannot be cleared by software, only by power-off or device reset. The Set Block Lock-down Bit command is a two-cycle command. At the first cycle, command (60H) and an address within the block to be locked-down is written to the target partition. At the second cycle, command (2FH) and the same address as the first cycle is written. Read operations to the target partition output the status register data until another valid command is written. After writing the second cycle command, the block lock-down bit is set within the minimum command cycle time and the corresponding block is locked-down. To check the lockdown status, write the Read Identifier Codes/OTP command (90H) and an address within the target block. Subsequent reads at Block Base Address +2 (see Table 6 through Table 8) will output the lock/unlock status of that block. The lock-down status is represented by the output pin DQ1. If the output of DQ1 is "1", the block lock-down bit is set correctly. Figure 11 shows set block lock-down bit flowchart.
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Bus Operation
Command
Comments
Write
Data=60H Addr=Within Block to be Clear Block Unlocked Lock Bit Data= D0H Addr=Within Block to be Unlocked Status Register Data Addr=Within Partition Check SR.4, 5 Both 1=Command Sequence Error Read ID Code Data=90H Addr=Within Partition Lock Bit Data Addr=Block Address+2 (see Table 6 through Table 8) Check DQ0 0=Lock Bit is Cleared
Read
Standby
Write
Read
Standby
Repeat for the subsequent clear block lock bit. Lock status check can be done after each clear block lock bit operation or after a sequence of clear block lock bit operations. SR.5 and SR.4 are only cleared by the Clear Status Register command in cases where multiple block lock bits are cleared before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Write FFH after a sequence of clear block lock bit operations to place device in read array mode.
Bus Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
Standby
Figure 12. Clear Block Lock Bit Flowchart
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The two-cycle command sequence ensures that block is not accidentally locked-down. An invalid Set Block Lock-down Bit command sequence will result in both status register bits SR.5 and SR.4 being set to "1" and the operation will not be executed. The Set Block Lock-down Bit command is available when the power supply voltage is specified level, independent of the voltage on VPP. At power-up or device reset, since no blocks are lockeddown, write the Set Block Lock-down Bit command as necessary. While WP# is VIH, the lock-down bits are disabled but not cleared. Once any block is locked-down, it cannot be cleared until power-off or device reset.
4.15 OTP Program Command
OTP program is executed by a two-cycle command sequence. At the first cycle, command (C0H) and an address within the OTP block (see Figure 4) is written, followed by the second write that specifies the address and data. After writing the command, the device outputs the status register data when any address within the device is selected. The WSM then takes over, controlling the internal OTP program algorithm. The system CPU can detect the OTP program completion by analyzing the output data of the status register bit SR.7. Figure 13.1 and Figure 13.2 show OTP program flowchart. The address written at the command cycle must be the address within the OTP block (refer to Figure 4). Writing an address outside the OTP block will cause a OTP program error and the status register bit SR.4 is set to "1". Clear the status register before writing next command. The internal WSM verify only detects errors for "1"s that are not successfully programmed to "0"s. Check the status register bit SR.4 at the end of OTP program. If a OTP program error is detected, the status register should be cleared before system software attempts corrective actions. For reliable OTP program operation, apply the specified voltage on VCC and VPPH1/2 on VPP. In the absence of this voltage, OTP program operations are not guaranteed. For example, attempting an OTP program at VPP VPPLK causes SR.4 and SR.3 being set to "1". OTP program operation on locked area causes SR.4 and SR.1 being set to "1" and the operation will not be executed. OTP program cannot be suspended through the (Page Buffer) Program Suspend command (B0H). Even if the (Page Buffer) Program Suspend command is written during OTP program operation, the suspend command will be ignored. If an error is detected during the OTP program operation, error bits for all status registers are set to "1". This requires that the Clear Status Register command be written to all partitions to clear the error bits. Dual work operation is not available while the OTP program mode, and the memory array data cannot be read even if that operation has been completed. To return to the read array mode, write the Read Array command (FFH) to the partition's CUI after the completion of the OTP program operation.
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Bus Operation
Command
Comments Data=C0H Addr=Location to be Programmed
Write
Write
OTP Program Data=Data to be Programmed Addr=Location to be Programmed Status Register Data Addr=X Check SR.7 1=WSM Ready 0=WSM Busy
Read
Standby
Repeat for subsequent OTP program. SR full status check can be done after each OTP program, or after a sequence of OTP programs. Write FFH after the OTP program operation to place device in read array mode.
Bus Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy
Standby
Figure 13.1. Automated OTP Program Flowchart
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Bus Operation Standby Standby Standby
Command
Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect Check SR.4 1=OTP Program Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Figure 13.2. Automated OTP Program Flowchart (Continued)
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4.16 Set Read Configuration Register Command
The Read Configuration Register (RCR) bits are set by writing the Set Read Configuration Register command to the device. This operation is initiated by a two-cycle command sequence. The read configuration register can be configured by writing the command with the read configuration register code. At the first cycle, command (60H) and a read configuration register code is written. At the second cycle, command (03H) and the same address as the first cycle is written. The read configuration register code is placed on the address bus, A15 - A0, and is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs first). The read configuration register code sets the device's read configuration, burst order, frequency configuration, and burst length. This command functions independently of the VPP voltage. RST# must be at VIH. After executing this command, the partition returns to read array mode. The read configuration register bits RCR.13-11, RCR.9, RCR.8, RCR.7, RCR.6, RCR.3 and RCR.2-0 are only valid for synchronous burst mode. Figure 16 shows set read configuration register flowchart.
NOTES: * The read configuration register code can be read via the Read Identifier Codes/OTP command (90H). Address 0005H on A15 - A0 contains the read configuration register code (see Table 6 through Table 8). * All the bits in the read configuration register are set to "1" after device power-up or reset. (Read configuration register bits are volatile.)
4.16.1 Device Read Configuration (Read Mode)
Each partition supports a high performance synchronous burst mode read configuration. The read configuration register bit RCR.15 sets the device read configuration (read mode; see Table 14). All the parameter and main blocks support asynchronous read mode, asynchronous 8-word page mode and synchronous burst mode configuration. Status register, query code, identifier codes, OTP block and configuration register codes can only be read in single asynchronous or single synchronous read mode.
Figure 14. Frequency Configuration
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Table 14. Read Configuration Register Definition RM 15 BS 7 R 14 CC 6 FC2 13 R 5 FC1 12 R 4 FC0 11 BW 3 R 10 BL2 2 DOC 9 BL1 1 WC 8 BL0 0
RCR.15 = READ MODE (RM) * 0 = Synchronous Burst Reads Enabled * 1 = Asynchronous Reads Enabled (Default) RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.13-11 = FREQUENCY CONFIGURATION (FC2-0) * 000 = Code 0 reserved for future use * 001 = Code 1 reserved for future use * 010 = Code 2 * 011 = Code 3 * 100 = Code 4 * 101 = Code 5 * 110 = Code 6 reserved for future use * 111 = Code 7 reserved for future use (Default) RCR.10 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.9 = DATA OUTPUT CONFIGURATION (DOC) * 0 = Hold Data for One Clock * 1 = Hold Data for Two Clocks (Default) RCR.8 = WAIT# CONFIGURATION (WC) * 0 = WAIT# Asserted During Delay * 1 = WAIT# Asserted One Data Cycle Before Delay (Default) RCR.7 = BURST SEQUENCE (BS) * 0 = Intel Burst Order * 1 = Linear Burst Order (Default) RCR.6 = CLOCK CONFIGURATION (CC) * 0 = Burst Starts and Data Output on Falling Clock Edge * 1 = Burst Starts and Data Output on Rising Clock Edge (Default) RCR.5-4 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.3 = BURST WRAP (BW) * 0 = Wrap Burst Reads within Burst Length set by RCR.2-0 * 1 = No Wrap Burst Reads within Burst Length set by RCR.2-0 (Default). RCR.2-0 = BURST LENGTH (BL2-0) * 001 = 4 Word Burst * 010 = 8 Word Burst * 011 = Reserved for future use * 111 = Continuous (Linear) Burst (Default)
NOTES: Read configuration register affects the read operations from main and parameter blocks. Read operations for status register, query code, identifier codes, OTP block and device configuration codes support single read cycles. RCR.14, RCR.10, RCR.5 and RCR.4 bits are reserved for future use. Refer to Frequency Configuration in Section 4.16.2 for information about the frequency configuration RCR.13-11. Undocumented combinations of bits RCR.13-11 are reserved by Sharp Corporation for future implementations and should not be used. Refer to Section 4.16.7 for information about Burst Wrap configuration RCR.3. In the asynchronous page mode, the burst length always equals 8 words. All the bits in the read configuration register are set to "1" after power-up or device reset. When the bit RCR.15 is set to "1", other bits are invalid.
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Table 15. Frequency Configuration Settings Read Configuration Register RCR.13 RCR.12 0 0 1 1 1 1 0 0 RCR.11 0 1 0 1 Frequency Configuration Code 2 3 4 5 Input Clock Frequency TBD ns 24MHz 36MHz 40MHz TBD MHz TBD ns TBD MHz TBD MHz TBD MHz TBD MHz
4.16.2 Frequency Configuration
The read configuration register bits RCR.13, RCR.12 and RCR.11 indicates the frequency configuration (see Table 14). The frequency configuration informs the number of clocks that must elapse after ADV# is driven active (VIL) before data will be available. This value is determined by the input clock frequency. See Table 15 for the specific input CLK frequency configuration. Figure 14 shows data output latency from ADV# going VIL for different frequency configuration codes.
4.16.3 Data Output Configuration
The data output configuration, shown by RCR.9 (see Table 14), determines the number of clocks that data will be held valid. The data hold time for the LH28F320BX/ LH28F640BX series can be set to one clock or two clocks (see Figure 15).
Figure 15. Output Configuration
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4.16.4 WAIT# Configuration
The WAIT# configuration bit RCR.8 (see Table 14) controls the WAIT# output signal. This output signal can be set to be asserted during or one CLK cycle before an output delay occurs, when the burst read crosses the first 64-word boundary in continuous burst length or the 4- or 8-word burst length with no-wrap mode. Its setting will depend on the system and CPU characteristic.
For example, if RCR.3="0" (wrap mode) and RCR.20=001 (4-word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1 and 3-0-1-2. If RCR.3="1" (no-wrap mode) and RCR.2-0=001 (4word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5 and 3-4-5-6. No-wrap mode not only enables limited non-aligned sequential burst, but also reduces power by minimizing the number of internal read operations.
4.16.5 Burst Sequence
The burst sequence bit RCR.7 (see Table 14) determines the order in which data is addressed in synchronous burst mode. This order is configurable to either linear or Intel burst order. The continuous burst length only supports linear burst order. The order will be determined by the CPU characteristic. Refer to Table 16 for linear burst order and Intel burst order in detail.
4.16.8 Burst Length
The burst length is the number of words that the device will output. The read configuration register bits RCR.2-0 (see Table 14) set the burst length. The LH28F320BX/ LH28F640BX series supports burst lengths of four and eight words. It also supports a continuous burst mode. In continuous burst mode, the device will linearly output data until the internal burst counter reaches the end of the device's burst-able address space or a partition boundary. Refer to Table 16 for burst length in detail.
4.16.6 Clock Configuration
The clock configuration bit RCR.6 (see Table 14) configures the device to start a burst cycle, output data, and assert WAIT# on the rising or falling edge of the clock. This CLK flexibility enables interfacing the LH28F320BX/LH28F640BX series Flash memory to a wide range of burst CPUs.
4.16.8.1 Continuous Burst Length
In continuous burst mode or 4-, 8-word burst with nowrap (RCR.3="1") mode, the flash memory may cause an output delay when the burst read crosses the first 64-word boundary. It depends on the starting address whether an output delay will occur or not. When the starting address is aligned to a 64-word boundary, the delay will not occur. If the starting address is the end of a 64-word boundary, the output delay will be equal to the frequency configuration setting; this is the worst case delay. The delay will only take place once during a continuous burst access. If the burst read never crosses a 64-word boundary, the delay will never happen. The WAIT# output pin is used in continuous burst mode or 4-, 8-word burst with no-wrap mode to inform the system if this output delay occurs.
4.16.7 Burst Wrap
The burst wrap bit RCR.3 (see Table 14) determines the wrap mode as follows. * 4- or 8-word burst-accesses are performed within the burst-length boundary in wrap mode (RCR.3="0"). * 4- or 8-word and continuous burst-accesses cross the burst-length boundaries in no-wrap mode (RCR.3="1"). No-wrap mode is only valid for linear burst order (RCR.7="1"). No-wrap mode (RCR.3="1") enables WAIT# to hold off the system processor, as it does in the continuous burst mode. In the no-wrap mode, the device operates similar to continuous linear burst mode but consumes less power during 4- and 8-word bursts. Refer to Table 16 for burst wrap in detail.
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Table 16. Read Sequence and Burst Length Starting Address [Decimal] 0 1 2 3 4 5 6 7 ... 14 15 ... 0 1 2 3 4 5 6 7 ... Burst Wrap(1) (RCR.3=) 0 0 0 0 0 0 0 0 ... ... ... 0 0 ... ... ... ... ... 1 1 1 1 1 1 1 1 ... ... ... 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 NA NA NA NA 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-1213 7-8-9-10-11-12-1314 ... NA NA NA NA NA NA NA NA ... Burst Addressing Sequence [Decimal] 4-Word Burst Length (RCR.2-0=001) Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Intel 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8-Word Burst Length (RCR.2-0=010) Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... Intel 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 ... Cotinuous Burst (RCR.2-0=111) Linear 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... 14-15-16-17-18-19-20... 15-16-17-18-19-20-21... 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20... 15-16-17-18-19-20-21... ... ...
14 15
1 1
NOTE: 1. The burst wrap bit (RCR.3) determines whether 4- or 8-word burst-accesses wrap within the burst-length boundary or whether they cross word-length boundaries to perform linear accesses. In the no-wrap mode (RCR.3=1), the device operates similar to continuous linear burst mode but consumes less power during 4- and 8-word bursts.
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Command
Comments Data=60H Addr=Configuration Register Code (see Table 14 or Table 17) Data= 03H (Read Configuration), or 04H(Partition Configuration) Addr=Configuration Register Code (see Table 14 or Table 17)
Write
Set Read Configuration Register, Set Partition Configuration Register
Write Read
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition Check SR.4, 5 Both 1=Command Sequence Error Read ID Code Data=90H Addr=Within Partition Read/Partition Configuration Register Code Addr=0005H/0006H (see Table 6 through Table 8) Check DQ15-DQ0 for Read/ Partition Configuration Register Code
Standby
Write
Read
Standby
Configuration register code can be read after set read/ partition configuration register operation. SR.5 and SR.4 are only cleared by the Clear Status Register command. If an error is detected, clear the status register before attempting retry or other error recovery. After a successful set read/partition configuration register operation, the device returns to read array mode.
Bus Operation Write Read
Command
Comments
Read Status Data=70H Register Addr=Within Partition Status Register Data Addr=Within Partition
Check SR.7 1=WSM Ready 0=WSM Busy Figure 16. Set Read Configuration Register and Set Partition Configuration Register Flowchart Standby
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4.17 Set Partition Configuration Register Command
The Partition Configuration Register (PCR) bits are set by writing the Set Partition Configuration Register command to the device. This operation is initiated by a two-cycle command sequence. The partition configuration register can be configured by writing the command with the partition configuration register code. At the first cycle, command (60H) and a partition configuration register code is written. At the second cycle, command (04H) and the same address as the first cycle is written. The partition configuration register code is placed on the address bus, A15 - A0, and is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs first). The partition configuration register code sets the partition boundaries. This command functions independently of the VPP voltage. RST# must be at VIH. After executing this command, the device returns to read array mode and status registers are cleared. Figure 16 shows set partition configuration register flowchart. NOTES: * The partition configuration register code can be read via the Read Identifier Codes/OTP command (90H). Address 0006H on A15 - A0 contains the partition configuration register code (see Table 6 through Table 8). * Partition configuration after device power-up or reset is as follows. (Partition configuration register bits are volatile.) Plane 0-2 are merged into one partition. (top parameter device) Plane1-3 are merged into one partition. (bottom parameter device)
4.17.1 Partition Configuration
The partition configuration shown in Table 17 determines the partiton boundaries for the dual work (simultaneous read while erase/program) operation. The partition boundaries can be set to any plane boundaries. If the partition configuration register bits PCR.10-8 (PC.2-0) are set to "001", the partition boundary is set between plane0 and plane1. There are two partitions in this configuration. Plane1-3 are merged to one partition. Status registers for plane1-3 are also merged to one. If the partition configuration register bits are set to "101", the partition boundaries are set between plane0 and plane1 and between plane2 and plane3. There are three partitions in this configuration. Plane1-2 are merged to one partition. If the partition configuration register bits are set to "111", there are four partitions. Each partition is just the same as each plane. Figure 17 illustrates the various partition configuration.
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Table 17. Partition Configuration Register Definition R 15 R 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 PC2 10 R 2 PC1 9 R 1 PC0 8 R 0
PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) * 000 = No partitioning. Dual Work is not allowed. * 001 = Plane1-3 are merged into one partition. (default in a bottom parameter device) * 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively. * 100 = Plane 0-2 are merged into one partition. (default in a top parameter device) * 011 = Plane 2-3 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. * 110 = Plane 0-1 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. * 101 = Plane 1-2 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions.
* 111 = There are four partitions in this configuration. Each plane corresponds to each partition respectively. Dual work operation is available between any two partitions. PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES: 1. After power-up or device reset, PCR10-8 (PC2-0) is set to "001" in a bottom parameter device and "100" in a top parameter device. 2. See Figure 17 for the detail on partition configuration. 3. PCR.15-11 and PCR.7-0 bits are reserved for future use. If these bits are read via the Read Identifier Codes/OTP command, the device may output "1" or "0" on these bits.
Figure 17. Partition Configuration
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5 Design Considerations 5.1 Hardware Design Considerations 5.1.1 Control using RST#, CE# and OE#
The device will often be used in large memory arrays. SHARP provides three control input pins to accommodate multiple memory connection. Three control input pins, RST#, CE# and OE# provide for: * Minimize the power consumption of the memory * Avoid data confliction on the data bus To effectively use these control input pins, access the desired memory by enabling the CE# through the address decoder. Connect OE# to READ# control signal of all memory devices and system. With these connections, the selected memory devices are activated and deselected memory devices are in standby mode. RST# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should toggle (once set to VIL) during system reset.
5.1.3 VPP Traces on Printed Circuit Boards
The VPP pin on the LH28F320BX/LH28F640BX series Flash memory is only used to monitor the power supply voltage and is not used for a power supply pin except for 12V supply. Therefore, even when on-board writing to the flash memory on the system, it is not required to consider that V PP supplies the currents on the printed circuit boards. However, in erase or program operations with applying 12V0.3V to VPP pin, VPP is used for the power supply pin. When executing these operations, VPP trace widths and layout should be similar to that of VCC to supply the flash memory cells current for erasing or programming. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
5.1.4 VCC, VPP, RST# Transitions
If VPP is lower than VPPLK, VCC is lower than VLKO, or RST# is not at VIH, block erase, full chip erase, (page buffer) program and OTP program operation are not guaranteed. When VPP error is detected, the status register bits SR.5 or SR.4 (depending on the attempted operation) and SR.3 will be set to "1". If RST# transitions to VIL during the block erase, full chip erase, (page buffer) program or OTP program operation, the status register bit SR.7 will remain "0" until reset operation has been completed. Then, the attempted operation will be aborted and the device will enter reset mode after the completion of the reset sequence. If RST# is taken VIL during a block erase, full chip erase, (page buffer) program or OTP program operation, the memory contents at the aborted location are no longer valid. Therefore, the proper command must be written again. And also, if VCC transitions to lower than VLKO during a block erase, full chip erase, (page buffer) program or OTP program operation, the attempted operation will be aborted and the memory contents at the aborted location are no longer valid. Write the proper command again after VCC transitions above VLKO.
5.1.2 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling for eliminating noises to the system power lines. System designers should consider standby current levels (ICCS), active current levels (ICCR) and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each VCC, VCCQ and GND and between VPP and GND (when VPP is used as 12V supply). These high-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. These capacitors will overcome voltage slumps caused by circuit board trace inductance.
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5.1.5 Power-Up/Down Protection
The LH28F320BX/LH28F640BX series is designed to offer protection against accidental block erase, full chip erase, (page buffer) program, OTP program due to noises during power transitions. When the device power-up, holding VPP and RST# to GND until VCC has reached the specified level and in stable. For additional information, please refer to the AP-007-SW-E RST#, VPP Electric Potential Switching Circuit. After power-up, the LH28F320BX/LH28F640BX series defaults to the mode described in Section 2.1. System designers must guard against spurious writes when VCC voltages are above VLKO and VPP voltages are above VPPLK, by referring to Section 5.3 and the following design considerations. Since both CE# and WE# must be at VIL for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection because alternation of memory contents can only occur after successful completion of the two-step command sequences. The individual block locking scheme, which enables each block to be independently locked, unlocked or lockeddown, prevents the accidental data alternation. The device is also disabled until RST# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset during power-up/down, invalid bus conditions can be masked, providing yet another level of memory protection.
5.1.7 Automatic Power Savings
Automatic Power Savings (APS) provides low-power operation during active mode. APS mode allows the flash memory to put itself into a low current state when not being accessed. After data is read from the memory array and addresses not switching, the device enters the APS mode where typical ICC current is comparable to ICCS. The flash memory stays in this static state with outputs valid until a new location is read. Standard address access timings (tAVQV ) provide new data when addresses are changed. During dual work operation (one partition being erased or programmed, while other partitions are one of read modes), the device cannot enter the APS mode even if the input address remains unchanged.
5.1.8 Reset Operation
During power-up/down or transitions of power supply voltage, hold the RST# pin at VIL to protect data against noises which are caused by invalid bus conditions and initialize the internal circuitry in flash memory. Bringing RST# to VIL resets the internal WSM (Write State Machine) and sets the status register to 80H. After return from reset, a time tPHQV is required until outputs are valid, and a delay, tPHWL and tPHEL, is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored.
5.1.6 Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. The LH28F320BX/LH28F640BX series' nonvolatility increases usable battery life because data is retained when system power is removed.
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5.2 Software Design Considerations 5.2.1 WSM (Write State Machine) Polling
The status register bit SR.7 provides a software method of detecting block erase, full chip erase, (page buffer) program and OTP program completion. After the Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command is written to the CUI (Command User Interface), SR.7 goes to "0". It will return to "1" when the WSM (Write State Machine) has completed the internal algorithm. The status register bit SR.7 is "1" state when the device is in the following mode. * The device can accept the next command. * Block erase is suspended and (page buffer) program operation is not executed. * (Page buffer) program is suspended. * Reset mode
5.3 Data Protection Method
Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto WE# signal or power supply, may be interpreted as false commands and causes undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: The below describes data protection method. 1) Protection of data in each block * ny locked block by setting its block lock bit is protected against the data alternation. When WP# is VIL, any locked-down block by setting its block lockdown bit is protected from lock status changes. By using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks). * For detailed block locking scheme, refer to Sections 4.12 to 4.14.
5.2.2 Attention to Program Operation
Do not re-program "0" data for the bit in which "0" has been already programmed. This re-program operation may generate the bit which cannot be erased. To change the data from "1" to "0", take the following steps. * Program "0" for the bit in which you want to change the data from "1" to "0". * Program "1" for the bit in which "0" has been already programmed. (When "1" is programmed, erase/program operations are not executed onto the memory cell in flash memory.) For example, changing the data from "10111101" to "10111100" requires "11111110" programmed.
2) Protection of data with VPP control * When the level of VPP is lower than VPPLK (VPP lockout voltage), write functions to all blocks including OTP block are disabled. All blocks are locked and the data in the blocks are completely protected. 3) Protection of data with RST# * Especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing RST# to VIL, which inhibits write operation to all blocks including OTP block. * For detailed description on RST# control, refer to Section 5.1.5. Protection against noises on WE# signal To prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on WE# signal.
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5.4 High Performance Read Mode 5.4.1 CPU Compatibility
LH28F320BX/LH28F640BX series supports two highperformance read modes for the parameter and main blocks: * Asynchronous read mode in which 8-word page mode is available * Synchronous burst mode These two read modes provide much higher read accesses than was previously used. The asynchronous read mode is suitable for non-clocked memory systems and is compatible with standard pagemode ROM. If the memory subsystem has access to an external processor referenced clock, the synchronous burst mode is available for increased read performance. The clock frequency for synchronous burst mode is described in specifications. If the system CPU or ASIC does not support page-mode or burst accesses, single asynchronous and synchronous read modes can be used. It depends on the setting in the read configuration register which read mode is available. When the read configuration register bit RCR.15 is set to "1", the device is in asynchronous read mode. If the bit RCR.15 is set to "0", the device is in synchronous burst mode. Upon reset, the device defaults to asynchronous read mode and is put into read array mode.
5.4.3 Address Latch
The internal address latch latches the address for read and write operations. The address latch is controlled by ADV#. When ADV# is VIL, the latch is open. The latch closes when ADV# is driven high or upon the first rising (or falling) edge of CLK while ADV# is VIL. This stores the current address on the bus into the flash memory device and lets the address bus change without affecting the flash. This pin works the same in write operations; the address to be written to the CUI is latched on the rising ADV# edge. Since write operations are asynchronous mode, CLK is ignored and the address is not latched on the clock edge. In asynchronous read mode, the address latch does not need to be used but addresses must then stay stable during the entire read operation. If ADV# is not used, which is fixed VIL, in asynchronous mode, addresses are latched on the rising edge of CE# during reads and on the rising edge of CE# or WE# whichever goes high first during writes.
5.4.4 Using Asynchronous Page Mode
After initial power-up or reset mode, the device defaults to asynchronous read mode in which 8-word page mode is available. The asynchronous page mode is available for the parameter and main blocks, and is not supported from other locations within the device, such as the status register, identifier codes, OTP block and query codes. In asynchronous page mode, CLK is ignored and ADV# must be held VIL throughout the page access. Holding ADV# VIL allows new page mode accesses. The initial valid address will store 8 words of data in the internal page buffer. Each word is then output onto the data bus by toggling the address A2-0. If the asynchronous page mode is only used, CLK and ADV# can be tied to GND. Holding CLK and ADV# GND will minimize the power consumed by these two pins and will simplify the interface, making it compatible with standard flash memory and industry standard page mode ROMs. With ADV# at VIL, the addresses cannot be latched into the device. Therefore, addresses must stay valid throughout the entire read cycle until CE# goes to VIH. Figure 18 shows a waveform for asynchronous page mode read timing with ADV# held low. Note that the address A2-0 must be toggled to output the page-mode data. In asynchronous read mode, the output of WAIT# is fixed to VOH.
5.4.2 Features of ADV# and CLK
ADV# and CLK pins are important for synchronous burst mode. * ADV# can be derived from the processor's transaction start signal. If the processor does not have this type of signal, other standard CPU control signals can be used to control ADV#. ADV# must toggle to inform the flash memory to latch a new address. If this signal is not used in asynchronous read mode, CE# must toggle to inform the flash memory of a new address. * CLK can be derived from the processor's memory clock output. If the processor does not supply this control signal to the memory subsystem, the signal can be received from the clock signal generator through a clock buffer. This buffer minimizes clock load and skew.
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5.4.5 Using Synchronous Burst Mode
Synchronous burst mode provides a performance increase over asynchronous read mode. It supports effective zero wait-state performance up to the frequency described in specifications. The synchronous burst mode is available for the parameter and main blocks, and is not supported from other locations within the device, such as the status register, identifier codes, OTP block and query codes. It is not possible to do a synchronous burst read across the partition boundary. Figure 19 illustrates a waveform for synchronous burst mode read timing. The valid addresses are asserted, and then the device will output the first data after certain delay time. Subsequent data will be output every CLK cycle. There are two different considerations for an external interface logic whether or not the processor supports synchronous burst mode at boot-up. * Case 1, the processor does not support synchronous burst mode at boot-up, but rather boots up in asynchronous read mode. This is the initial mode of the flash memory, so no special design considerations need to be made. After booting up, the processor can configure the read configuration register for synchronous burst mode. * Case 2, the processor does support synchronous burst mode at boot-up. After return from reset, the flash memory defaults to asynchronous read mode, which is inherently slower than synchronous burst mode. External interface logic will be needed to inform the processor of this, and to insert wait states to match the flash memory's timing with the processor's timing. This logic is only necessary until the processor has a chance to set the flash memory device to synchronous burst mode, at which time the external logic must be notified of this change. This can be accomplished via a write-able register within the system wait-state logic or via a general purpose I/O (GPIO) pin. The GPIO pin may operate as an input into the system logic.
When the output delay is encountered, the WAIT# pin will be asserted at a logic "0". This signal should be fed into the systems wait-state control logic or directly to the CPU. The WAIT# output pin is gated by CE# and OE#. If either CE# or OE# go to VIH, the WAIT# output buffer turns off. An internal pull-up resistor holds WAIT# at a logic "1" state. Figure 20 shows a waveform for an output delay timing with ADV# at a logic "0". WAIT# can be configured for assertion during the delay or one data cycle before the delay by setting the read configuration register bit RCR.8.
5.4.7 Single Read Mode
The following data can only be read in single asynchronous read mode or single synchronous read mode. * Status register * Query code * Manufacturer code * Device code * Block lock configuration code * Read configuration register code * Partition configuration register code * OTP block A waveform of read timing for single asynchronous read mode and single synchronous read mode are shown in Figure 21 and Figure 22, respectively. Single asynchronous read mode is compatible with previous SHARP flash memory devices. CLK is ignored in this mode. The valid addresses are asserted, and then the device will output data after certain delay time, such as tAVQV, tVLQV, tELQV or t GLQV. Addresses are latched on the rising edge of ADV#. If ADV# is held VIL, addresses must stay valid throughout the entire read cycle until CE# goes to VIH. In single synchronous read mode, after the valid addresses are asserted, the corresponding data will be output on the rising or falling edge of CLK, which is determined by the read configuration register bit RCR.6. Addresses are lathed when ADV# is driven high or upon the rising or falling edge of CLK while ADV# is VIL. 4word, 8-word or continuous burst accesses is not available in this mode. Therefore, the external input addresses must be incremented every read cycle.
5.4.6 Using WAIT# in Burst Mode
LH28F320BX/LH28F640BX series supports 4-word, 8word and continuous burst modes. In continuous burst mode or 4-, 8-word burst with no-wrap (RCR.3="1") mode, WAIT# informs the system CPU whether output data is valid or not (refer to Section 4.16.8.1). * WAIT#="1": there is valid data on the bus. * WAIT#="0": the data on the bus is invalid.
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Figure 18. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks (A21 is not used for 32M-bit device.)
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Figure 19. AC Waveform for Synchronous Burst Mode Read Operations from Main Blocks or Parameter Blocks in 4-Word Burst Mode: RCR.2-0=001 (A21 is not used for 32M-bit device.)
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Figure 20. AC Waveform for an Output Delay when Continuous Burst Read with Data Output Configurations Set to One Clock (A21 is not used for 32M-bit device.)
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Figure 21. AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code (A21 is not used for 32M-bit device.)
Rev. 2.20 |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| Rev 2.20 Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13318 Model No.: LRS1381 March 16, 2001
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Figure 22. AC Waveform for Single Synchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code (A21 is not used for 32M-bit device.)
Rev. 2.20 |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| Rev 2.20 Synchronous burst mode will be available for future device.
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6 Common Flash Interface
This section defines the data structure of the Common Flash Interface (CFI) code, which is called query code. Query code can be read by writing the Read Query command (98H) to the target partition's CUI. System software should confirm this code to gain critical information such as block size, density, bit organization and electrical specifications. Once this code has been obtained, the software will understand which command sets should be used to enable erases, programs and other operations for the flash memory device. The query code is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface or CFI. Common Flash Interface for the LH28F320BX/ LH28F640BX series is now under development. Query code is described in the next version of Appendix.
Rev. 2.20 |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| Rev 2.20
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7 Related Document Information(1)
Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E
Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, VPP Electric Potential Switching Circuit
NOTE: 1. International customers should contact their local SHARP or distribution sales office.
Rev. 2.20 |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| |||||||||||||||||||||||||| Rev 2.20
Appendix to Spec No.: MFM2-J13318 Model No.: LRS1381 March 16, 2001

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